Abstract: According to one embodiment, a semiconductor device includes: a first frame, a second frame spaced apart from the first frame in a first direction, and a first joint terminal provided above a second chip provided on the second frame. The first frame includes a first terminal portion extending toward the second frame. The first joint terminal includes a second terminal portion extending toward the first frame. The second terminal portion includes a plane portion, a first projecting portion and a second projecting portion each branching out from the plane portion. An end portion of the first projecting portion and an end portion of the second projecting portion are respectively joined on the first terminal portion. The first projecting portion is different in a length in a first direction from the second projecting portion.

Abstract: According to one embodiment, a semiconductor device includes: a semiconductor chip including a first surface, a second surface, a first electrode, a second electrode, and a third electrode; a first conductor including a first portion and a first intermediate portion, a second conductor including a third portion, a second intermediate portion, and a fourth portion, and a length of the first intermediate portion in a second direction being longer than a length of the third portion in the second direction; a third conductor provided on a first surface side of the semiconductor chip; a conductive first connector provided between the first intermediate portion of the first conductor and the third portion of the second conductor; a conductive second connector provided between the second electrode and the first portion; and a conductive third connector provided between the third conductor and the first electrode.

Abstract: To reduce a package size of a semiconductor device. According to embodiments, there is a semiconductor device comprising: a first die pad; a first inner lead arranged inside a molded resin; a second die pad; and a second inner lead arranged inside the resin, wherein a part of the first inner lead and a part of the second inner lead are adhered and electrically connected to each other, a first semiconductor chip mounted on the first die pad is electrically connected to a second semiconductor chip mounted on the second die pad via the first inner lead and the second inner lead, and an end face of one end of the first inner lead and the second inner lead that are adhered to each other is exposed to a side surface of the resin.

Abstract: According to one embodiment, a method for determining layout of an element includes selecting, among stress distribution information of a semiconductor chip, stress distribution information of a stress component in a same direction as a current that flows through an element placed in the semiconductor chip, calculating, from the selected stress distribution information, a stress value at a coordinate at which the element is placed, and calculating, from the stress value, a score according to a degree of influence of characteristics fluctuation of the element due to the stress.

Abstract: To reduce a package size of a semiconductor device. According to embodiments, there is a semiconductor device comprising: a first die pad; a first inner lead arranged inside a molded resin; a second die pad; and a second inner lead arranged inside the resin, wherein a part of the first inner lead and a part of the second inner lead are adhered and electrically connected to each other, a first semiconductor chip mounted on the first die pad is electrically connected to a second semiconductor chip mounted on the second die pad via the first inner lead and the second inner lead, and an end face of one end of the first inner lead and the second inner lead that are adhered to each other is exposed to a side surface of the resin.

Abstract: According to embodiments, there is a semiconductor device comprising: a first die pad; a first inner lead arranged inside a molded resin; a second die pad; and a second inner lead arranged inside the resin, wherein a part of the first inner lead and a part of the second inner lead are adhered and electrically connected to each other, a first semiconductor chip mounted on the first die pad is electrically connected to a second semiconductor chip mounted on the second die pad via the first inner lead and the second inner lead, and an end face of one end of the first inner lead and the second inner lead that are adhered to each other is exposed to a side surface of the resin.

Abstract: To reduce a package size of a semiconductor device. According to embodiments, there is a semiconductor device comprising: a first die pad; a first inner lead arranged inside a molded resin; a second die pad; and a second inner lead arranged inside the resin, wherein a part of the first inner lead and a part of the second inner lead are adhered and electrically connected to each other, a first semiconductor chip mounted on the first die pad is electrically connected to a second semiconductor chip mounted on the second die pad via the first inner lead and the second inner lead, and an end face of one end of the first inner lead and the second inner lead that are adhered to each other is exposed to a side surface of the resin.

Abstract: According to one embodiment, there is provided a printed circuit board including a substrate having a trench between a first region and a second region. The first region is a region where a first package is to be mounted. The second region is a region where a second package is to be mounted. The trench has an opening portion in at least one of a first main surface and a second main surface of the substrate. The first main surface is a surface on which the first package is placed. The second main surface is positioned on reverse side of the first main surface of the substrate.

Abstract: According to one embodiment, there is provided a printed circuit board including a substrate having a trench between a first region and a second region. The first region is a region where a first package is to be mounted. The second region is a region where a second package is to be mounted. The trench has an opening portion in at least one of a first main surface and a second main surface of the substrate. The first main surface is a surface on which the first package is placed. The second main surface is positioned on reverse side of the first main surface of the substrate.

Abstract: According to one embodiment, a package substrate design device includes a first wiring module, a net generator, a second wiring module, and a third wiring module. The first wiring module is configured to generate a plurality of first vias configured to connect wires on the first wiring layer and wires on the second wiring layer and configured to generate a plurality of first wires configured to connect the first vias and the first terminals. The net generator is configured to generate nets for connecting the second terminals and k-th (k is an integer of 1 to (n?2)) vias. The second wiring module is configured to generate a plurality of (k+1)-th vias configured to connect wires on the (k+1)-th wiring layer and wires on the (k+2)-th wiring layer and configured to generate a plurality of (k+1)-th wires configured to connect the (k+1)-th vias and the k-th vias, the (k+1)-th vias and the (k+1)-th wires being generated between the k-th vias and the second terminals connected by the nets.

Abstract: A system for designing connecting terminals of a semiconductor device, having a power supply cell arranging unit configured to arrange power supply cells at some of I/O slots formed in a semiconductor chip, an I/O signal cell arranging unit configured to arrange I/O signal cells at some of the I/O slots where the power supply cells are not arranged, a first connecting net generator configured to generate a first connecting net connecting the I/O slots to bumps formed on the semiconductor chip, a second connecting net generator configured to generate a second connecting net connecting the bumps to external electrodes formed on a package base, and a verifier configured to verify whether the power supply cells, I/O signal cells, and first and second connecting nets violate predetermined design rules.

Abstract: A system for designing connecting terminals of a semiconductor device, having a power supply cell arranging unit configured to arrange power supply cells at some of I/O slots formed in a semiconductor chip, an I/O signal cell arranging unit configured to arrange I/O signal cells at some of the I/O slots where the power supply cells are not arranged, a first connecting net generator configured to generate a first connecting net connecting the I/O slots to bumps formed on the semiconductor chip, a second connecting net generator configured to generate a second connecting net connecting the bumps to external electrodes formed on a package base, and a verifier configured to verify whether the power supply cells, I/O signal cells, and first and second connecting nets violate predetermined design rules.