Patents by Inventor Toyoki Asada

Toyoki Asada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9065368
    Abstract: In order to cause the residual magnetic flux in an induction motor to decay in a short time without an excessive current flow, an induction motor control apparatus continues an operation in which an inverter apparatus is caused to output a zero voltage to the induction motor for a predetermined time before deactivating an operation of the inverter apparatus.
    Type: Grant
    Filed: February 13, 2013
    Date of Patent: June 23, 2015
    Assignee: HITACHI, LTD.
    Inventors: Shuichi Tachihara, Tetsuo Kojima, Toyoki Asada, Yongqiang Xia
  • Publication number: 20130257343
    Abstract: In order to cause the residual magnetic flux in an induction motor to decay in a short time without an excessive current flow, an induction motor control apparatus continues an operation in which an inverter apparatus is caused to output a zero voltage to the induction motor for a predetermined time before deactivating an operation of the inverter apparatus.
    Type: Application
    Filed: February 13, 2013
    Publication date: October 3, 2013
    Applicant: HITACHI, LTD.
    Inventors: Shuichi TACHIHARA, Tetsuo KOJIMA, Toyoki ASADA, Yongqiang XIA
  • Patent number: 6635971
    Abstract: An electronic device, in which terminals of a semiconductor integrated circuit chip and terminals of a circuit substrate are mounted with solder so as to face one another. The electronic device includes a first resin, which is disposed between the circuit substrate and a terminal formation face of the semiconductor integrated circuit chip and a second resin, which is disposed at the outer perimeter of the semiconductor integrated circuit chip or is disposed laterally thereon. The modulus of elasticity of the second resin is smaller than the modulus of elasticity of the first resin, the modulus of elasticity of the second resin is at least 0.5 GPa but not more than 28 GPa at room temperature.
    Type: Grant
    Filed: January 11, 2002
    Date of Patent: October 21, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Toyoki Asada, Yuji Fujita, Hideo Sotokawa, Kazumi Kawamoto, Kunio Matsumoto, Shinya Hamagishi, Mari Matsuyoshi
  • Patent number: 6589802
    Abstract: The present invention a structure in which a semiconductor integrated circuit chip can be easily removed and the reliability of flip-chip bonding is assured, a method of packaging electronic parts, and method and apparatus for detaching electronic parts. According to the invention, the object is achieved by a flip-chip bonding structure using two kinds of soluble and insoluble resins for bonding a semiconductor integrated circuit chip and a circuit board.
    Type: Grant
    Filed: August 18, 2000
    Date of Patent: July 8, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Toyoki Asada, Yuji Fujita, Kie Ueda, Naoya Kanda, Mari Matsuyoshi
  • Publication number: 20020090162
    Abstract: An electronic device, in which terminals of a semiconductor integrated circuit chip and terminals of a circuit substrate are mounted with solder so as to face one another. The electronic device includes a first resin, which is disposed between the circuit substrate and a terminal formation face of the semiconductor integrated circuit chip and a second resin, which is disposed at the outer perimeter of the semiconductor integrated circuit chip or is disposed laterally thereon. The modulus of elasticity of the second resin is smaller than the modulus of elasticity of the first resin, the modulus of elasticity of the second resin is at least 0.5 GPa but not more than 28 GPa at room temperature.
    Type: Application
    Filed: January 11, 2002
    Publication date: July 11, 2002
    Inventors: Toyoki Asada, Yuji Fujita, Hideo Sotokawa, Kazumi Kawamoto, Kunio Matsumoto, Shinya Hamagishi, Mari Matsuyoshi
  • Patent number: 6153938
    Abstract: A stable low-connecting resistance connection arrangement having a high yield rate without using any special material or process for a substrate. A flip-chip connecting structure in which the semiconductor integrated circuit (IC) chip is mounted directly on an organic circuit substrate. To achieve reliable connection and low-connecting resistance, the present invention absorbs variation of the heights of projecting electrodes formed on a semiconductor IC chip and substrate electrodes of an organic circuit substrate for example, by deforming the substrate electrodes and/or substrate layer of the organic circuit substrate. Resin of a conductive paste disposed between the projecting electrodes and substrate electrodes is squeezed out leaving a high density conductive particle layer to lower a contact resistance between such electrodes.
    Type: Grant
    Filed: July 27, 1998
    Date of Patent: November 28, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Naoya Kanda, Toyoki Asada, Yoshio Oozeki, Yasuo Amano, Kunio Matsumoto, Yasuhiro Narikawa