Abstract: Use of a custom insert is obviated when a digital camera is attached to a base (dock). Two movable pins are provided, in such a way that a connector is sandwiched between the movable pins, on a digital camera attachment surface of a base (dock) which provides a digital camera with a recharging function and a printing function. The movable pins fit to holes in a bottom of the digital camera to thus act as guides during the course of attachment of the digital camera. Alternatively, the attachment surface itself may be configured so as to be vertically movable, and the attachment surface may descend during attachment of the digital camera and the attachment surface may be latched in a lower position after attachment of the same.

Abstract: Use of a custom insert is obviated when a digital camera is attached to a base (dock). Two movable pins are provided, in such a way that a connector is sandwiched between the movable pins, on a digital camera attachment surface of a base (dock) which provides a digital camera with a recharging function and a printing function. The movable pins fit to holes in a bottom of the digital camera to thus act as guides during the course of attachment of the digital camera. Alternatively, the attachment surface itself may be configured so as to be vertically movable, and the attachment surface may descend during attachment of the digital camera and the attachment surface may be latched in a lower position after attachment of the same.

Abstract: Use of a custom insert is obviated when a digital camera is attached to a base (dock). Two movable pins are provided, in such a way that a connector is sandwiched between the movable pins, on a digital camera attachment surface of a base (dock) which provides a digital camera with a recharging function and a printing function. The movable pins fit to holes in a bottom of the digital camera to thus act as guides during the course of attachment of the digital camera. Alternatively, the attachment surface itself may be configured so as to be vertically movable, and the attachment surface may descend during attachment of the digital camera and the attachment surface may be latched in a lower position after attachment of the same.

Abstract: Use of a custom insert is obviated when a digital camera is attached to a base (dock). Two movable pins are provided, in such a way that a connector is sandwiched between the movable pins, on a digital camera attachment surface of a base (dock) which provides a digital camera with a recharging function and a printing function. The movable pins fit to holes in a bottom of the digital camera to thus act as guides during the course of attachment of the digital camera. Alternatively, the attachment surface itself may be configured so as to be vertically movable, and the attachment surface may descend during attachment of the digital camera and the attachment surface may be latched in a lower position after attachment of the same.

Abstract: Use of a custom insert is obviated when a digital camera is attached to a base (dock). Two movable pins are provided, in such a way that a connector is sandwiched between the movable pins, on a digital camera attachment surface of a base (dock) which provides a digital camera with a recharging function and a printing function. The movable pins fit to holes in a bottom of the digital camera to thus act as guides during the course of attachment of the digital camera. Alternatively, the attachment surface itself may be configured so as to be vertically movable, and the attachment surface may descend during attachment of the digital camera and the attachment surface may be latched in a lower position after attachment of the same.

Abstract: A first-in, first-out (FIFO) type buffer circuit is positioned to hold write-data between a random access memory and a system data bus. A shift circuit is positioned between an address calculation circuit and a pointer circuit. The system data bus is connected to an output of the FIFO buffer circuit or a read-data circuit of the random access memory dependent on an operation mode between writing and reading modes, and the pointer circuit is connected to the address calculation circuit or the shift circuit dependent on the operation mode. Accordingly, pipeline control is realized, even if the data transfer and the memory processing are reversed in order between the writing and reading modes.

Abstract: A microcomputer comprises an instruction buffer receiving an instruction, a first decoder for decoding the instruction outputted from instruction buffer so as to generate a write request detection signal, an instruction memory for receiving and storing the instruction outputted from instruction buffer, a program counter for indicating an address to be written or read, a second instruction decoder for receiving an instruction code read from the instruction memory and for generating data and control signals including a halt signal, a data memory for storing the data from the second instruction decoder in response to a write signal from the second instruction decoder and for outputting data stored in the data memory in response to a read signal from the second instruction decoder, an address counter for receiving an address information from the second instruction decoder and for supplying an address to the data memory, a logic circuit connected to receive through a gate the halt signal from the second instructio

Abstract: A disc control apparatus comprises a first register for storing a first track position which is presently traced, a second register for storing a second track position which is next to be traced, a first memory for storing a first rotating number of a disc under a seek operation, and a second memory for storing a second rotating number of the disc at a settling time. The first track position is an upper address signal for the first memory, and a lower address signal for the first memory is produced in accordance with a subtraction between the first and second track positions, so that the first memory is accessed at an address composed of the upper and lower addresses to produce the first rotating number signal. The second memory is accessed at an address determined solely by the first track position to produce the second rotating number signal.

Abstract: An address control circuit for a data memory includes a first register for temporarily storing address information applied thereto and for supplying the stored address information to the data memory, a second register for temporarily storing write address information, a third register for temporarily storing offset address information, a write address control circuit coupled to the first and second registers for supplying to the first register address information relative to the write address information and for updating the content of the second register in a data write operation, and a read address control circuit coupled to the first to third registers for producing read address information corresponding to a difference between the content of the second register and the offset address information and for supplying the read address information to the first register in a data read operation.

Abstract: An overflow correction circuit is coupled to receive an output of an arithmetic operation circuit having first and second data inputs. The first data input is connected to an internal data bus so as to receive data to be subjected to an arithmetic operation, and the output of the arithmetic operation circuit outputs a result of arithmetic operation. The overflow correction circuit comprises a selector having a first input connected to receive the result of arithmetic operation from the arithmetic operation circuit and a second input and an output, a corrected value generating circuit having an output connected to the second input of the first selector, an overflow detection circuit coupled to receive the output of the arithmetic operation circuit and for generating an overflow signal indicative of whether or not there occurs an overflow in the result of the arithmetic operation.

Abstract: A data processing apparatus comprises a program counter for designating the address of a microinstruction to be read. A decoder receives the microinstruction stored in the address designated by the program counter and generates at least a first selection signal, a second selection signal, a first register address signal and a number-of-counter-selection signal. A first counter receives a first timing signal to count the first timing signal when the first selection signal is active so that the first counter generates a second register address signal incremented at each occurrence of the first timing signal. A multiplexer receives the first and second register address signals to select and output the second register address when the first selection signal is active. A register group including a plurality of registers is responsive to the first timing signal to latch the output of the multiplexer so as to select a register designated by the output of the multiplexer.