Patents by Inventor Toyoyuki Shimazaki
Toyoyuki Shimazaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7298977Abstract: The present invention is intended to prevent a light-emitting diode from emitting light continuously in the case when the level at an input terminal is fixed high because of software or the like and to avoid various problems, such as battery exhaustion and breakdown of the light-emitting diode, in PDAs, cellular phones, etc. For these purposes, a high-pass filter 21 for passing the high-frequency components of an optical transmission input signal having a pulse waveform and a binary circuit 22 for binarizing the output signal of the high-pass filter 21 so as to be returned to a pulse waveform are provided in the preceding stage of a light-emitting device driving circuit 23 for driving a light-emitting diode 8 for optical transmission.Type: GrantFiled: November 28, 2002Date of Patent: November 20, 2007Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Katsuichi Ohsawa, Toyoyuki Shimazaki, Tetsuo Chato, Yuzo Shimizu, Kenji Imaizumi
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Publication number: 20050063710Abstract: The present invention is intended to prevent a light-emitting diode from emitting light continuously in the case when the level at an input terminal is fixed high because of software or the like and to avoid various problems, such as battery exhaustion and breakdown of the light-emitting diode, in PDAs, cellular phones, etc. For these purposes, a high-pass filter 21 for passing the high-frequency components of an optical transmission input signal having a pulse waveform and a binary circuit 22 for binarizing the output signal of the high-pass filter 21 so as to be returned to a pulse waveform are provided in the preceding stage of a light-emitting device driving circuit 23 for driving a light-emitting diode 8 for optical transmission.Type: ApplicationFiled: November 28, 2002Publication date: March 24, 2005Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Katsuichi Ohsawa, Toyoyuki Shimazaki, Tetsuo Chato, Yuzo Shimizu, Kenji Imaizumi
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Patent number: 6700144Abstract: A semiconductor device includes the following: a semiconductor substrate of a first conduction type; an intrinsic semiconductor layer of the first conduction type formed on the semiconductor substrate; a first semiconductor layer of a second conduction type formed on the intrinsic semiconductor layer; a first impurity layer of the first conduction type formed in the first semiconductor layer of the second conduction type; and a bipolar transistor and a MIS transistor formed in the first semiconductor layer of the second conduction type. The laminated structure of the semiconductor substrate, the intrinsic semiconductor layer, and the first semiconductor layer provides a diode for photoelectric conversion. A first insulator layer and a second insulator layer are formed respectively in at least a portion below the bipolar transistor and the MIS transistor.Type: GrantFiled: May 24, 2002Date of Patent: March 2, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Toyoyuki Shimazaki, Katuichi Ohsawa, Tetsuo Chato, Yuzo Shimizu
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Patent number: 6492665Abstract: After a gate insulating film, a gate electrode and an on-gate protective layer have been formed in this order on an Si substrate, lightly-doped source/drain regions are formed in the substrate. First and second sidewalls are formed on the sides of the gate electrode and then heavily-doped source/drain regions are formed by implanting dopant ions using these sidewalls as a mask. After the second sidewall has been selectively removed, pocket implanted regions are formed and an overall protective film is deposited. Thereafter, an interlevel dielectric film is deposited, contact holes are formed to reach the heavily-doped source/drain regions and then plug electrodes are formed. Since the second sidewall has already been removed when the overall protective film is deposited, the gap between adjacent gate electrodes is not completely filled in.Type: GrantFiled: November 17, 2000Date of Patent: December 10, 2002Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Susumu Akamatsu, Toshitaka Hibi, Takehiko Ueda, Tadami Shimizu, Yoshiaki Kato, Tatsuya Obata, Toyoyuki Shimazaki
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Publication number: 20020182801Abstract: A semiconductor device includes the following: a semiconductor substrate of a first conduction type; an intrinsic semiconductor layer of the first conduction type formed on the semiconductor substrate; a first semiconductor layer of a second conduction type formed on the intrinsic semiconductor layer; a first impurity layer of the first conduction type formed in the first semiconductor layer of the second conduction type; and a bipolar transistor and a MIS transistor formed in the first semiconductor layer of the second conduction type. The laminated structure of the semiconductor substrate, the intrinsic semiconductor layer, and the first semiconductor layer provides a diode for photoelectric conversion. A first insulator layer and a second insulator layer are formed respectively in at least a portion below the bipolar transistor and the MIS transistor.Type: ApplicationFiled: May 24, 2002Publication date: December 5, 2002Applicant: Matsushita Electric Industrial Co., LtdInventors: Toyoyuki Shimazaki, Katuichi Ohsawa, Tetsuo Chato, Yuzo Shimizu
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Patent number: 6180472Abstract: After a gate insulating film, a gate electrode and an on-gate protective layer have been formed in this order on an Si substrate, lightly-doped source/drain regions are formed in the substrate. First and second sidewalls are formed on the sides of the gate electrode and then heavily-doped source/drain regions are formed by implanting dopant ions using these sidewalls as a mask. After the second sidewall has been selectively removed, pocket implanted regions are formed and an overall protective film is deposited. Thereafter, an interlevel dielectric film is deposited, contact holes are formed to reach the heavily-doped source/drain regions and then plug electrodes are formed. Since the second sidewall has already been removed when the overall protective film is deposited, the gap between adjacent gate electrodes is not completely filled in.Type: GrantFiled: July 27, 1999Date of Patent: January 30, 2001Assignee: Matsushita Electrons CorporationInventors: Susumu Akamatsu, Toshitaka Hibi, Takehiko Ueda, Tadami Shimizu, Yoshiaki Kato, Tatsuya Obata, Toyoyuki Shimazaki