Abstract: Apparatus and methods are presented for using configurable additive data scrambling or descrambling circuitry for multichannel link aggregators in which a scrambler or descrambler polynomial is specified by binary data in a programmable register, and the polynomial data is used to compute a polynomial matrix. A scrambler or descrambler pattern is computed according to the polynomial matrix, and input data is bitwise exclusive-ORed with the computed scrambler or descrambler pattern to generate scrambled or descrambled output data. The scrambling or descrambling circuitry can be reconfigured for different polynomials by reprogramming the register, with the scrambler or descrambler automatically computing an updated polynomial matrix.

Abstract: One example includes network physical link (PHY) switch system. The system includes a multiplexer to output a first of a plurality of data streams that are input to a PHY device in response to a first state of a selection signal. The system also includes a data detector that monitors the first data stream and provides a trigger signal in response to a predetermined condition associated with the first data stream. The system further includes a switching controller that provides the selection signal, and in response to a switching command signal indicating a command to switch from the first data stream to the second data stream, monitors the data detector for the trigger signal and changes the selection signal from the first state to a second state in response to receiving the trigger signal to switch to the second data stream of the plurality of data streams.

Abstract: Apparatus and methods are presented for using configurable additive data scrambling or descrambling circuitry for multichannel link aggregators in which a scrambler or descrambler polynomial is specified by binary data in a programmable register, and the polynomial data is used to compute a polynomial matrix. A scrambler or descrambler pattern is computed according to the polynomial matrix, and input data is bitwise exclusive-ORed with the computed scrambler or descrambler pattern to generate scrambled or descrambled output data. The scrambling or descrambling circuitry can be reconfigured for different polynomials by reprogramming the register, with the scrambler or descrambler automatically computing an updated polynomial matrix.

Abstract: One example includes network physical link (PHY) switch system. The system includes a multiplexer to output a first of a plurality of data streams that are input to a PHY device in response to a first state of a selection signal. The system also includes a data detector that monitors the first data stream and provides a trigger signal in response to a predetermined condition associated with the first data stream. The system further includes a switching controller that provides the selection signal, and in response to a switching command signal indicating a command to switch from the first data stream to the second data stream, monitors the data detector for the trigger signal and changes the selection signal from the first state to a second state in response to receiving the trigger signal to switch to the second data stream of the plurality of data streams.

Abstract: An apparatus is provided. Physical medium dependent (PMD) sublayer logic is configured to communicate with a communications medium. Physical medium attachment (PMA) sublayer logic is coupled to the PMD logic. Forward error correction (FEC) sublayer logic is coupled to the PMA sublayer logic, and physical coding (PCS) sublayer logic is configured to communicate with an interface. A transmit path is coupled to the transmit data in a second clock domain to the FEC sublayer logic. A first read pointer circuit is coupled to transmit path. A write pointer circuit is coupled to the transmit path. A receive path is coupled to receive data in the second clock domain from the FEC sublayer logic. A second read pointer circuit is coupled to the receive path, where the first read pointer circuit, the second read pointer circuit, and the write pointer circuits are each configured to detect gaps between the first and second clock domains.

Abstract: An apparatus is provided. Physical medium dependent (PMD) sublayer logic is configured to communicate with a communications medium. Physical medium attachment (PMA) sublayer logic is coupled to the PMD logic. Forward error correction (FEC) sublayer logic is coupled to the PMA sublayer logic, and physical coding (PCS) sublayer logic is configured to communicate with an interface. A transmit path is coupled to the transmit data in a second clock domain to the FEC sublayer logic. A first read pointer circuit is coupled to transmit path. A write pointer circuit is coupled to the transmit path. A receive path is coupled to receive data in the second clock domain from the FEC sublayer logic. A second read pointer circuit is coupled to the receive path, where the first read pointer circuit, the second read pointer circuit, and the write pointer circuits are each configured to detect gaps between the first and second clock domains.

Abstract: As part of the protocol for Common Public Radio Interface/Open Base Station Architecture Initiative (CPRI/OBSAI) systems, timing circuits are used to calculate the “round trip” latency across CPRI/OBSAI links. Traditionally, these timing circuits have been plagued with numerous problems. Here, however, a timing circuit is provided that has improved latency measurement accuracy, reduced power consumption, and a reduced likelihood of detecting a false comma. This is generally accomplished through the use of double edge latching in combination with post processing circuit and single bit transmission between low and high speed clock domains.

Abstract: As part of the protocol for Common Public Radio Interface/Open Base Station Architecture Initiative (CPRI/OBSAI) systems, multiple data rates are supported, which are each supported by one or more reference clock frequencies. Traditionally, timing circuits presently used for the physical layer (PHY) paths to determine the data rates for the serial data have been plagued with numerous problems. Here, however, a circuit that performs an automatic rate sense (ARS) of high speed serial signals in a low speed digital domain is provided, which is also relatively easy to implement and robust.

Abstract: As part of the protocol for Common Public Radio Interface/Open Base Station Architecture Initiative (CPRI/OBSAI) systems, multiple data rates are support, which are each supported by one or more reference clock frequencies. Traditionally, timing circuits present used for the physical layer (PHY) paths to determine the data rates for the serial data have been plagued with numerous problems. Here, however, a circuit that performs an automatic rate sense (ARS) of high speed serial signals in a low speed digital domain is provided, which is also relatively easy to implement and robust.

Abstract: As part of the protocol for Common Public Radio Interface/Open Base Station Architecture Initiative (CPRI/OBSAI) systems, timing circuits are used to calculate the “round trip” latency across CPRI/OBSAI links. Traditionally, these timing circuits have been plagued with numerous problems. Here, however, a timing circuit is provided that has improved latency measurement accuracy, reduced power consumption, and a reduced likelihood of detecting a false comma. This is generally accomplished through the use of double edge latching in combination with post processing circuit and single bit transmission between low and high speed clock domains.

Abstract: A method is provided. In this method, a clock signal and an input signal are received, where the input signal is a Manchester encoded signal. A unit interval (UI) number is incremented for each UI received upon receipt of a valid UI. The UI number is compared to a plurality of threshold values after the each increment of the UI number, where each threshold value is associated with at least one of a plurality of sum values. For each threshold value, once exceeded by the UI number, its sum value is incremented for each cycle of the clock signal, and a plurality of window lengths are calculated, where each window is calculated based at least in part on at least one of the sum values at predetermined values of the UI number.

Abstract: A method is provided. In this method, a clock signal and an input signal are received, where the input signal is a Manchester encoded signal. A unit interval (UI) number is incremented for each UI received upon receipt of a valid UI. The UI number is compared to a plurality of threshold values after the each increment of the UI number, where each threshold value is associated with at least one of a plurality of sum values. For each threshold value, once exceeded by the UI number, its sum value is incremented for each cycle of the clock signal, and a plurality of window lengths are calculated, where each window is calculated based at least in part on at least one of the sum values at predetermined values of the UI number.

Abstract: A method for decoding a Manchester-II encoded DISPLAYPORT compatible signal is provided. In this method, several counters are reset. A unit interval (UI) counter is incremented for each UI received upon receipt of a valid UI, and the value of the UI counter is compared to a plurality of threshold values after the UI counter is incremented. When the value of the UI counter exceeds each of the threshold values, for each clock cycle, a sum counter is incremented corresponding to the exceeded threshold value, and a plurality of window lengths are calculated, where each window is calculated based at least in part on the value of one of the sum counters at predetermined values of the UI counter.

Abstract: A method for decoding a Manchester-II encoded DISPLAYPORT compatible signal is provided. In this method, several counters are reset. A unit interval (UI) counter is incremented for each UI received upon receipt of a valid UI, and the value of the UI counter is compared to a plurality of threshold values after the UI counter is incremented. When the value of the UI counter exceeds each of the threshold values, for each clock cycle, a sum counter is incremented corresponding to the exceeded threshold value, and a plurality of window lengths are calculated, where each window is calculated based at least in part on the value of one of the sum counters at predetermined values of the UI counter.

Abstract: A computer program (100, 200) encoded in a computer-programmable medium, and for causing a computer to perform circuit design. The code causes the computer to perform a set of steps. The steps comprise describing a first set of circuitry and describing a second set of circuitry. The steps also comprise describing a digital signal for passing from the first set of circuitry to the second set of circuitry and detecting (230) transitions of the digital signal with respect to a timing constraint (240) of at least a portion of the second set of circuitry. Lastly, the steps comprise, responsive to detecting metastability with respect to timing of a transition of the digital signal relative to the timing constraint of at least a portion of the second set of circuitry, forcing (160) the digital signal to a random value and passing the random value to the second set of circuitry.

Abstract: An electronic device (10). The device comprises a memory structure (12) comprising an integer M of word storage locations. The device further comprises a write shift register (SRWT) for storing a sequence of bits. The sequence in the write shift register comprises a number of bits equal to a ratio of 1/R1 times the integer M. The device further comprises circuitry (16) for providing a write clock cycle to the write shift register for selected write operations with respect to any of the word storage locations. In response to each write clock cycle, received from the circuitry for providing the write clock cycle, the write shift register shifts the sequence in the write shift register. Further, one bit in the sequence in the write shift register corresponds to an indication of one of the memory word storage locations into which a word will be written. The device further comprises a read shift register (SRRD) for storing a sequence of bits.

Abstract: An electronic device (10). The device comprises a memory structure (12) structure comprising an integer M of word storage locations. The device further comprises a shift register (SRRD; SRWT) for storing a sequence of bits. The sequence in the shift register comprises a number of bits equal to a ratio of 1/R1 times the integer M. The device further comprises circuitry (16) for providing a clock cycle to the shift register for selected data operations with respect to any of the word storage locations. The selected data operations are a data read or a data write. In response to each clock cycle, received from the circuitry for providing the clock cycle, the shift register shifts the sequence. Further, one bit in the sequence corresponds to an indication of one of the memory word storage locations from which a word will be read or into which a word will be written.