Patents by Inventor Trace Hurd
Trace Hurd has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230092779Abstract: In one example, a method for wafer drying includes providing a surface of a first wafer, the surface of the first wafer including a liquid to be removed with a drying process. The method further includes replacing the liquid with a first solid film in a first processing chamber, the first solid film covering the surface of the first wafer. The method further includes transferring the first wafer from the first processing chamber to a second processing chamber. The method further includes processing the first wafer in the second processing chamber by flowing a supercritical fluid through the second processing chamber, where the supercritical fluid removes the first solid film.Type: ApplicationFiled: November 23, 2022Publication date: March 23, 2023Inventors: Trace Hurd, Antonio Luis Pacheco Rotondaro, Derek William Bassett, Hitoshi Kosugi
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Patent number: 11515178Abstract: In one example, a method for wafer drying includes providing a surface of a first wafer, the surface of the first wafer including a liquid to be removed with a drying process. The method further includes replacing the liquid with a first solid film in a first processing chamber, the first solid film covering the surface of the first wafer. The method further includes transferring the first wafer from the first processing chamber to a second processing chamber. The method further includes processing the first wafer in the second processing chamber by flowing a supercritical fluid through the second processing chamber, where the supercritical fluid removes the first solid film.Type: GrantFiled: March 16, 2020Date of Patent: November 29, 2022Assignee: Tokyo Electron LimitedInventors: Trace Hurd, Antonio Luis Pacheco Rotondaro, Derek William Bassett, Hitoshi Kosugi
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Publication number: 20210287919Abstract: In one example, a method for wafer drying includes providing a surface of a first wafer, the surface of the first wafer including a liquid to be removed with a drying process. The method further includes replacing the liquid with a first solid film in a first processing chamber, the first solid film covering the surface of the first wafer. The method further includes transferring the first wafer from the first processing chamber to a second processing chamber. The method further includes processing the first wafer in the second processing chamber by flowing a supercritical fluid through the second processing chamber, where the supercritical fluid removes the first solid film.Type: ApplicationFiled: March 16, 2020Publication date: September 16, 2021Inventors: Trace Hurd, Antonio Luis Pacheco Rotondaro, Derek William Bassett, Hitoshi Kosugi
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Patent number: 10886290Abstract: A method of etching a substrate includes providing an etching solution in a tank of an etch processing system, where the etch processing system is configured to control temperature of the etching solution, a concentration of the etching solution, and flow of the etching solution within the tank. The substrate contains micro-fabricated structures that have alternating layers of a first material and a second material, and the etching solution including an acid that etches the first material and results in an etch product to be moved from the substrate. The method further includes monitoring a concentration of the etch product within the etching solution, and maintaining the concentration of the etch product within the etching solution below a predetermined value to prevent deposition of the etch product on the second material in an amount that blocks etching of the first material by the etching solution.Type: GrantFiled: July 19, 2019Date of Patent: January 5, 2021Assignee: Tokyo Electron LimitedInventors: Derek Bassett, Antonio Rotondaro, Ihsan Simms, Trace Hurd
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Patent number: 10844332Abstract: An alkaline wet solution for protecting features on a patterned substrate and a substrate processing method using the alkaline wet solution are described. The method includes providing a patterned substrate containing a low-k material, a metal oxide feature, and an etch residue, performing a treatment process that exposes the patterned substrate to an alkaline wet solution that forms a protective coating on the metal oxide feature, the alkaline wet solution containing a mixture of 1) water, 2) ammonium hydroxide, a quaternary organic ammonium hydroxide, or a quaternary organic phosphonium hydroxide, and 3) dissolved silica, and performing a wet cleaning process that removes the etch residue but not the metal oxide feature that is protected by the protective coating. The patterned substrate can further include a metallization layer and the alkaline wet solution can further contain 4) an inhibitor that protects the metallization layer from etching by the alkaline wet solution.Type: GrantFiled: December 14, 2018Date of Patent: November 24, 2020Assignee: Tokyo Electron LimitedInventors: Takayuki Toshima, Hiroshi Marumoto, Yoshinori Nishiwaki, Trace Hurd
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Publication number: 20200027891Abstract: A method of etching a substrate includes providing an etching solution in a tank of an etch processing system, where the etch processing system is configured to control temperature of the etching solution, a concentration of the etching solution, and flow of the etching solution within the tank. The substrate contains micro-fabricated structures that have alternating layers of a first material and a second material, and the etching solution including an acid that etches the first material and results in an etch product to be moved from the substrate. The method further includes monitoring a concentration of the etch product within the etching solution, and maintaining the concentration of the etch product within the etching solution below a predetermined value to prevent deposition of the etch product on the second material in an amount that blocks etching of the first material by the etching solution.Type: ApplicationFiled: July 19, 2019Publication date: January 23, 2020Inventors: Derek Bassett, Antonio Rotondaro, Ihsan Simms, Trace Hurd
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Publication number: 20190185793Abstract: An alkaline wet solution for protecting features on a patterned substrate and a substrate processing method using the alkaline wet solution are described. The method includes providing a patterned substrate containing a low-k material, a metal oxide feature, and an etch residue, performing a treatment process that exposes the patterned substrate to an alkaline wet solution that forms a protective coating on the metal oxide feature, the alkaline wet solution containing a mixture of 1) water, 2) ammonium hydroxide, a quaternary organic ammonium hydroxide, or a quaternary organic phosphonium hydroxide, and 3) dissolved silica, and performing a wet cleaning process that removes the etch residue but not the metal oxide feature that is protected by the protective coating. The patterned substrate can further include a metallization layer and the alkaline wet solution can further contain 4) an inhibitor that protects the metallization layer from etching by the alkaline wet solution.Type: ApplicationFiled: December 14, 2018Publication date: June 20, 2019Inventors: Takayuki Toshima, Hiroshi Marumoto, Yoshinori Nishiwaki, Trace Hurd
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Publication number: 20170345665Abstract: A processing apparatus includes a processing chamber having a substrate holder; a first gas delivery system configured to deliver a first source gas within the processing chamber; a second gas delivery system configured to deliver a second source gas within the processing chamber; an energy activation system; and processing circuitry. The processing circuitry is configured to control first processing parameters for delivery of the first source gas, control second processing parameters for delivery of the second source gas, control processing chamber parameters and energy activation system parameters to cause a reaction of the first source gas and the second source gas with a surface of one or more parts in the processing chamber to etch an atomic layer from the surface of the one or more parts in absence of a plasma, and control vacuum system parameters for removal of one or more reaction gases from the processing chamber.Type: ApplicationFiled: May 24, 2017Publication date: November 30, 2017Applicant: Tokyo Electron LimitedInventors: Jacques FAGUET, Trace Hurd, Ian Brown
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Patent number: 7732345Abstract: The present invention provides a method for manufacturing an integrated circuit. In one embodiment, the method includes etching one or more openings within a substrate using an etch tool, and subjecting the one or more openings to a post-etch clean, wherein a delay time exists between removing the substrate from the etch tool and the subjecting the one or more opening to the post-etch clean. This method may further include exposing the substrate having been subjected to the post-etch clean to a rinsing agent, wherein a resistivity of the rinsing agent is selected based upon the delay time.Type: GrantFiled: August 31, 2006Date of Patent: June 8, 2010Assignee: Texas Instruments IncorporatedInventors: Phillip Daniel Matz, Trace Hurd
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Publication number: 20080057730Abstract: The present invention provides a method for manufacturing an integrated circuit. In one embodiment, the method includes etching one or more openings within a substrate using an etch tool, and subjecting the one or more openings to a post-etch clean, wherein a delay time exists between removing the substrate from the etch tool and the subjecting the one or more opening to the post-etch clean. This method may further include exposing the substrate having been subjected to the post-etch clean to a rinsing agent, wherein a resistivity of the rinsing agent is selected based upon the delay time.Type: ApplicationFiled: August 31, 2006Publication date: March 6, 2008Applicant: Texas Instruments IncorporatedInventors: Phillip Daniel Matz, Trace Hurd
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Publication number: 20080020558Abstract: The present invention provides a method for patterning a metal gate electrode and a method for manufacturing an integrated circuit including the same. The method for patterning the metal gate electrode, among other steps, includes forming a metal gate electrode layer (220) over a gate dielectric layer (210) located on a substrate (110), and patterning the gate electrode layer (220) using a combination of a dry etch process (410) and a wet etch process (510).Type: ApplicationFiled: September 26, 2007Publication date: January 24, 2008Applicant: Texas Instruments IncorporatedInventors: Antonio Rotondaro, Deborah Riley, Trace Hurd
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Publication number: 20070249168Abstract: A semiconductor device 100 comprising a gate structure 105 on a semiconductor substrate 110 and a recessed-region 115 in the semiconductor substrate. The recessed-region has a widest lateral opening 120 that is near a top surface 122 of the semiconductor substrate. The widest lateral opening undercuts the gate structure.Type: ApplicationFiled: April 20, 2006Publication date: October 25, 2007Applicant: Texas Instruments IncorporatedInventors: Antonio Rotondaro, Trace Hurd, Elisabeth Koontz
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Publication number: 20060115972Abstract: The present invention provides a method for patterning a metal gate electrode and a method for manufacturing an integrated circuit including the same. The method for patterning the metal gate electrode, among other steps, includes forming a metal gate electrode layer (220) over a gate dielectric layer (210) located on a substrate (110), and patterning the gate electrode layer (220) using a combination of a dry etch process (410) and a wet etch process (510).Type: ApplicationFiled: November 29, 2004Publication date: June 1, 2006Applicant: Texas Instruments, Inc.Inventors: Antonio Rotondaro, Deborah Riley, Trace Hurd
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Publication number: 20060035463Abstract: A method of preparing a die comprises treating exposed silicon to form an oxide prior to silicide formation; and depositing metal on the oxide. The metal may comprise titanium, cobalt, nickel, platinum, palladium, tungsten, molybdenum, or combinations thereof on the oxide. The oxide may be less than or equal to about 15 angstroms thick. In various embodiments, treating exposed silicon to form an oxide comprises forming a non- thermal oxide. Treating exposed silicon to form an oxide may also comprise treating the exposed silicon with an oxidizing plasma; alternatively, treating exposed silicon to form an oxide may comprise forming a chemical oxide. In certain other embodiments, treating exposed silicon to form an oxide comprises treating exposed silicon with a solution comprising ammonium hydroxide, hydrogen peroxide, and water; hydrochloric acid, hydrogen peroxide, and water; hydrogen peroxide; ozone; ozonated deionized water; or combinations thereof.Type: ApplicationFiled: August 10, 2004Publication date: February 16, 2006Applicant: Texas Instruments IncorporatedInventors: Sue Crank, Shirin Siddiqui, Deborah Riley, Trace Hurd, Peijun Chen
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Publication number: 20060024972Abstract: The present invention provides a process of manufacturing a semiconductor device 200 while reducing silicon loss. In one aspect, the process includes removing a photoresist layer 270 from a semiconductor substrate 235 adjacent a gate 240 and cleaning the semiconductor substrate with a wet clean solution. The removing step includes subjecting the photoresist layer 270 to a plasma ash. The plasma ash removes at least a portion of a crust 275 formed on the photoresist layer 270 but leaves a substantial portion of the photoresist layer 270. The photoresist layer 270 is subjected to a wet etch subsequent to the plasma ash that removes a substantial portion of the photoresist layer 270.Type: ApplicationFiled: July 29, 2004Publication date: February 2, 2006Applicant: Texas Instruments IncorporatedInventors: Lindsey Hall, Trace Hurd, Deborah Riley
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Publication number: 20050260853Abstract: The present invention provides, in one embodiment, a method of forming a copper layer (100) over a semiconductor substrate (105). The method comprises coating a copper seed layer (110) located over a semiconductor substrate with a protective agent (120) to form a protective layer (125). The method also includes placing the semiconductor substrate in an acid bath (145) to remove the protective layer. The method further includes electrochemically depositing a second copper layer (155) on the copper seed layer. Such methods and resulting conductive structures thereof may be advantageously used in methods to manufacture integrated circuits comprising copper interconnects.Type: ApplicationFiled: May 18, 2004Publication date: November 24, 2005Applicant: Texas Instruments, IncorporatedInventors: Sanjeev Aggarwal, Lindsey Hall, Trace Hurd
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Publication number: 20050233586Abstract: A trench and via structure is formed in a low k dielectric layer (100) formed over a silicon substrate (10). Super critical CO2 and a first silylization agent are used to form a chemically bonded high density surface layer (160). Silanol species are removed from the low k dielectric layer (100) using super critical CO2 and a second silylization agent. A barrier layer (190) and copper (200) are used to fill the trench and via structure.Type: ApplicationFiled: July 27, 2004Publication date: October 20, 2005Inventors: Phillip Matz, Sameer Ajmera, Changming Jin, Trace Hurd