Patents by Inventor Trace Q. Hurd
Trace Q. Hurd has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20110316089Abstract: A semiconductor device comprises a gate structure on a semiconductor substrate and a recessed region in the semiconductor substrate. The recessed region has a widest lateral opening that is near a top surface of the semiconductor substrate. The widest lateral opening undercuts the gate structure.Type: ApplicationFiled: September 9, 2011Publication date: December 29, 2011Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Antonio Luis PACHECO ROTONDARO, Trace Q. HURD, Elisabeth Marley KOONTZ
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Publication number: 20110318901Abstract: A semiconductor device comprises a gate structure on a semiconductor substrate and a recessed region in the semiconductor substrate. The recessed region has a widest lateral opening that is near a top surface of the semiconductor substrate. The widest lateral opening undercuts the gate structure.Type: ApplicationFiled: September 9, 2011Publication date: December 29, 2011Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Antonio Luis Pacheco ROTONDARO, Trace Q. HURD, Elisabeth Marley KOONTZ
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Patent number: 8049254Abstract: A semiconductor device comprises a gate structure on a semiconductor substrate and a recessed region in the semiconductor substrate. The recessed region has a widest lateral opening that is near a top surface of the semiconductor substrate. The widest lateral opening undercuts the gate structure.Type: GrantFiled: March 23, 2009Date of Patent: November 1, 2011Assignee: Texas Instruments IncorporatedInventors: Antonio Luis Pacheco Rotondaro, Trace Q. Hurd, Elisabeth Marley Koontz
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Publication number: 20090174005Abstract: A semiconductor device comprises a gate structure on a semiconductor substrate and a recessed region in the semiconductor substrate. The recessed region has a widest lateral opening that is near a top surface of the semiconductor substrate. The widest lateral opening undercuts the gate structure.Type: ApplicationFiled: March 23, 2009Publication date: July 9, 2009Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Antonio Luis Pacheco Rotondaro, Trace Q. Hurd, Elisabeth Marley Koontz
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Patent number: 7528072Abstract: A semiconductor device comprising a gate structure on a semiconductor substrate and a recessed-region in the semiconductor substrate. The recessed-region has a widest lateral opening that is near a top surface of the semiconductor substrate. The widest lateral opening undercuts the gate structure.Type: GrantFiled: April 20, 2006Date of Patent: May 5, 2009Assignee: Texas Instruments IncorporatedInventors: Antonio Luis Pacheco Rotondaro, Trace Q. Hurd, Elisabeth Marley Koontz
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Patent number: 7422969Abstract: The present invention provides a method for patterning a metal gate electrode and a method for manufacturing an integrated circuit including the same. The method for patterning the metal gate electrode, among other steps, includes forming a metal gate electrode layer (220) over a gate dielectric layer (210) located on a substrate (110), and patterning the gate electrode layer (220) using a combination of a dry etch process (410) and a wet etch process (510).Type: GrantFiled: September 26, 2007Date of Patent: September 9, 2008Assignee: Texas Instruments IncorporatedInventors: Antonio L. P. Rotondaro, Deborah J. Riley, Trace Q. Hurd
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Patent number: 7371691Abstract: The present invention provides a process of manufacturing a semiconductor device 200 while reducing silicon loss. In one aspect, the process includes removing a photoresist layer 270 from a semiconductor substrate 235 adjacent a gate 240 and cleaning the semiconductor substrate with a wet clean solution. The removing step includes subjecting the photoresist layer 270 to a plasma ash. The plasma ash removes at least a portion of a crust 275 formed on the photoresist layer 270 but leaves a substantial portion of the photoresist layer 270. The photoresist layer 270 is subjected to a wet etch subsequent to the plasma ash that removes a substantial portion of the photoresist layer 270.Type: GrantFiled: July 29, 2004Date of Patent: May 13, 2008Assignee: Texas Instruments IncorporatedInventors: Lindsey H. Hall, Trace Q. Hurd, Deborah J. Riley
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Patent number: 7323403Abstract: The present invention provides a method for patterning a metal gate electrode and a method for manufacturing an integrated circuit including the same. The method for patterning the metal gate electrode, among other steps, includes forming a metal gate electrode layer (220) over a gate dielectric layer (210) located on a substrate (110), and patterning the gate electrode layer (220) using a combination of a dry etch process (410) and a wet etch process (510).Type: GrantFiled: November 29, 2004Date of Patent: January 29, 2008Assignee: Texas Instruments IncroporatedInventors: Antonio L. P. Rotondaro, Deborah J. Riley, Trace Q. Hurd
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Patent number: 7195679Abstract: The present invention provides a system (200, 300) for remediating aberrations along the perimeter of a semiconductor wafer (202). The system includes a cleaning apparatus (204) within which the wafer is spun within a confined area. A chuck (208) defines the confined area, having a sidewall that extends above the upper surface (214) of the wafer and surrounds the perimeter of the wafer. The chuck also has a bottom wall, with an aperture formed therein, beneath the wafer. The system includes an isolation barrier (220), disposed atop the bottom wall of the chuck and around the aperture, in proximity to the lower surface so of the wafer. This forms a narrow gap (226) between the barrier and the wafer. A pressurized source forcefully directs a gas (218) at and along the lower surface of the wafer. The system also includes a remediation solution (228) that is applied to the upper surface of the wafer.Type: GrantFiled: June 21, 2003Date of Patent: March 27, 2007Assignee: Texas Instruments IncorporatedInventors: Changfeng Xia, Trace Q. Hurd
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Patent number: 7037823Abstract: A trench and via structure is formed in a low k dielectric layer (100) formed over a silicon substrate (10). Super critical CO2 and a first silylization agent are used to form a chemically bonded high density surface layer (160). Silanol species are removed from the low k dielectric layer (100) using super critical CO2 and a second silylization agent. A barrier layer (190) and copper (200) are used to fill the trench and via structure.Type: GrantFiled: July 27, 2004Date of Patent: May 2, 2006Assignee: Texas Instruments IncorporatedInventors: Phillip D. Matz, Sameer Ajmera, Changming Jin, Trace Q. Hurd
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Patent number: 6995088Abstract: The present invention provides, in one embodiment, a method of forming a copper layer (100) over a semiconductor substrate (105). The method comprises coating a copper seed layer (110) located over a semiconductor substrate with a protective agent (120) to form a protective layer (125). The method also includes placing the semiconductor substrate in an acid bath (145) to remove the protective layer. The method further includes electrochemically depositing a second copper layer (155) on the copper seed layer. Such methods and resulting conductive structures thereof may be advantageously used in methods to manufacture integrated circuits comprising copper interconnects.Type: GrantFiled: May 18, 2004Date of Patent: February 7, 2006Assignee: Texas Instruments IncorporatedInventors: Sanjeev Aggarwal, Lindsey Hall, Trace Q. Hurd
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Publication number: 20040255985Abstract: The present invention provides a system (200, 300) for remediating aberrations along the perimeter of a semiconductor wafer (202). The system includes a cleaning apparatus (204) within which the wafer is spun within a confined area. A chuck (208) defines the confined area, having a sidewall that extends above the upper surface (214) of the wafer and surrounds the perimeter of the wafer. The chuck also has a bottom wall, with an aperture formed therein, beneath the wafer. The system includes an isolation barrier (220), disposed atop the bottom wall of the chuck and around the aperture, in proximity to the lower surface so of the wafer. This forms a narrow gap (226) between the barrier and the wafer. A pressurized source forcefully directs a gas (218) at and along the lower surface of the wafer. The system also includes a remediation solution (228) that is applied to the upper surface of the wafer.Type: ApplicationFiled: June 21, 2003Publication date: December 23, 2004Inventors: Changfeng Xia, Trace Q. Hurd
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Patent number: 6709875Abstract: A ferroelectric device fabrication process is described in which ferroelectric device contaminant substances (e.g., Pb, Zr, Ti, and Ir) that are incompatible with standard CMOS fabrication processes are tightly controlled. In particular, specific etch chemistries have been developed to remove incompatible substances from the backside and edge surfaces of the substrate after a ferroelectric device has been formed. In addition, a sacrificial layer may be disposed over the bottom and edge surfaces (and, in some embodiments, the frontside edge exclusion zone surface) of the substrate to assist in the removal of difficult-to-etch contaminants (e.g., Ir). In this way, the ferroelectric device fabrication process may be integrated with a standard semiconductor fabrication process, whereby ferroelectric devices may be formed together with semiconductor integrated circuits without substantial risk of cross-contamination through shared equipment (e.g., steppers, metrology tools, and the like).Type: GrantFiled: August 8, 2001Date of Patent: March 23, 2004Assignees: Agilent Technologies, Inc., Texas Instruments, Inc.Inventors: Stephen R. Gilbert, Trace Q. Hurd, Laura W. Mirkarimi, Scott Summerfelt, Luigi Colombo
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Publication number: 20030036209Abstract: A ferroelectric device fabrication process is described in which ferroelectric device contaminant substances (e.g., Pb, Zr, Ti, and Ir) that are incompatible with standard CMOS fabrication processes are tightly controlled. In particular, specific etch chemistries have been developed to remove incompatible substances from the backside and edge surfaces of the substrate after a ferroelectric device has been formed. In addition, a sacrificial layer may be disposed over the bottom and edge surfaces (and, in some embodiments, the frontside edge exclusion zone surface) of the substrate to assist in the removal of difficult-to-etch contaminants (e.g., Ir). In this way, the ferroelectric device fabrication process may be integrated with a standard semiconductor fabrication process, whereby ferroelectric devices may be formed together with semiconductor integrated circuits without substantial risk of cross-contamination through shared equipment (e.g., steppers, metrology tools, and the like).Type: ApplicationFiled: August 8, 2001Publication date: February 20, 2003Inventors: Stephen R. Gilbert, Trace Q. Hurd, Laura W. Mirkarimi, Scott Summerfelt, Luigi Colombo