Patents by Inventor Trace Quentin Hurd

Trace Quentin Hurd has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11376640
    Abstract: In one exemplary embodiment, described herein are innovative techniques for reducing the attractive force between particles and a substrate surface to aid in the removal of particles from the substrate surface. More specifically, a multi-electrode chuck is utilized to assist in cleaning a substrate. The multi-electrode chuck is utilized to reduce the attractive forces between particles and the substrate and to move the loosened particles that are present on the substrate surface. The electrodes of the chuck are biased with alternating current (AC) voltages with a phase shift between the electrode bias waves. The resulting electric field wave on the substrate surface loosens the particles by polarizing the particles and moves the loosened particles across the substrate.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: July 5, 2022
    Assignee: Tokyo Electron Limited
    Inventors: Antonio Luis Pacheco Rotondaro, Derek Bassett, Trace Quentin Hurd, Ihsan Simms
  • Publication number: 20210384049
    Abstract: A wet etch system comprises an etching bath comprising an etching solution in a process tank inside an overflow tank flowing over an open top into the overflow tank. The etching bath has a top cover, a gas inlet, and a gas outlet above the etching solution. A gas flow system pumps inert gas into the gas inlet and extracts the gas through the gas outlet under positive pressure. The gas flow system may also bubble inert gas through the etching solution via injectors of a gas sparger in the process tank. A recirculation path connects a liquid outlet port coupled to the overflow tank to a liquid inlet port coupled to the process tank. A pump drives the etching solution to flow from the overflow tank, through a degasser in the recirculation path, back into the process tank, and overflow from the process tank into the overflow tank.
    Type: Application
    Filed: November 3, 2020
    Publication date: December 9, 2021
    Inventors: Derek William Bassett, Antonio Luis Pacheco Rotondaro, Trace Quentin Hurd, Hironobu Hyakutake, Kazuyoshi Mizumoto, Nobuaki Matsumoto
  • Publication number: 20200101500
    Abstract: In one exemplary embodiment, described herein are innovative techniques for reducing the attractive force between particles and a substrate surface to aid in the removal of particles from the substrate surface. More specifically, a multi-electrode chuck is utilized to assist in cleaning a substrate. The multi-electrode chuck is utilized to reduce the attractive forces between particles and the substrate and to move the loosened particles that are present on the substrate surface. The electrodes of the chuck are biased with alternating current (AC) voltages with a phase shift between the electrode bias waves. The resulting electric field wave on the substrate surface loosens the particles by polarizing the particles and moves the loosened particles across the substrate.
    Type: Application
    Filed: September 17, 2019
    Publication date: April 2, 2020
    Inventors: Antonio Luis Pacheco Rotondaro, Derek Bassett, Trace Quentin Hurd, Ihsan Simms
  • Publication number: 20150045277
    Abstract: A cleaning composition and process for cleaning post-chemical mechanical polishing (CMP) residue and contaminants from a microelectronic device having said residue and contaminants thereon. The cleaning compositions include at least one quaternary base, at least one amine, at least one azole corrosion inhibitor, at least one reducing agent, and at least one solvent. The composition achieves highly efficacious cleaning of the post-CMP residue and contaminant material from the surface of the microelectronic device while being compatible with barrier layers, wherein the barrier layers are substantially devoid of tantalum or titanium.
    Type: Application
    Filed: March 14, 2013
    Publication date: February 12, 2015
    Applicant: Entegris, Inc.
    Inventors: Jun Liu, Trace Quentin Hurd, Laisheng Sun, Steven Medd, Shrane Ning Jenq
  • Publication number: 20110117751
    Abstract: Composition and method to remove undoped silicon-containing materials from microelectronic devices at rates greater than or equal to the removal of doped silicon-containing materials.
    Type: Application
    Filed: March 6, 2009
    Publication date: May 19, 2011
    Applicant: ADVANCED TECHNOLOGY MATERIALS, INC.
    Inventors: Prerna Sonthalia, Emanuel I. Cooper, David Minsek, Peng Zhang, Melissa A. Petruska, Brittany Serke, Trace Quentin Hurd
  • Patent number: 7132365
    Abstract: A method of preparing a die comprises treating exposed silicon to form an oxide prior to silicide formation; and depositing metal on the oxide. The metal may comprise titanium, cobalt, nickel, platinum, palladium, tungsten, molybdenum, or combinations thereof on the oxide. The oxide may be less than or equal to about 15 angstroms thick. In various embodiments, treating exposed silicon to form an oxide comprises forming a non-thermal oxide. Treating exposed silicon to form an oxide may also comprise treating the exposed silicon with an oxidizing plasma; alternatively, treating exposed silicon to form an oxide may comprise forming a chemical oxide. In certain other embodiments, treating exposed silicon to form an oxide comprises treating exposed silicon with a solution comprising ammonium hydroxide, hydrogen peroxide, and water; hydrochloric acid, hydrogen peroxide, and water; hydrogen peroxide; ozone; ozonated deionized water; or combinations thereof.
    Type: Grant
    Filed: August 10, 2004
    Date of Patent: November 7, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Sue Ellen Crank, Shirin Siddiqui, Deborah J. Riley, Trace Quentin Hurd, Peijun J. Chen
  • Patent number: 6787425
    Abstract: Methods are presented for fabricating MOS transistors, in which a sacrificial material such as silicon germanium is formed over a gate contact material prior to gate patterning. The sacrificial material is then removed following sidewall spacer formation to provide a recess at the top of the gate structure. The recess provides space for optional epitaxial silicon formation and suicide formation over the gate contact material without overflowing the tops of the sidewall spacers to minimize shorting between the gate and the source/drains in the finished transistor.
    Type: Grant
    Filed: June 16, 2003
    Date of Patent: September 7, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Antonio Luis Pacheco Rotondaro, Trace Quentin Hurd, Stephanie Watts Butler, Majid M. Mansoori