Patents by Inventor Tracy Garrett Drysdale

Tracy Garrett Drysdale has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6976155
    Abstract: A method and apparatus for synchronizing and communicating between processing entities, such as cores or threads, in a multiprocessor. Two registers are used as a “hardware mailbox” by two processing entities of a microprocessor. A first register is used to communicate information from a first processing entity to a second processing entity, while a second register is used to communication information from the second processing entity to the first processing entity. The first and second registers are cross-decoded by the two processing entities. One or more bits in each register are used to synchronize operation of the processing entities. In a microprocessor including three or more such processing entities, a read-write register of each processing entity holds outgoing information and a read-only register of each processing entity holds incoming information. A separate logic circuit logically combines the contents of the read-write registers and stores the result in the read-only registers.
    Type: Grant
    Filed: June 12, 2001
    Date of Patent: December 13, 2005
    Assignee: Intel Corporation
    Inventors: Tracy Garrett Drysdale, Scott P Bobholz
  • Publication number: 20040030957
    Abstract: Various methods, apparatuses, and systems that use a replacement policy algorithm to implement tracking of one or more memory locations that have incurred one or more data transfer failures.
    Type: Application
    Filed: August 12, 2002
    Publication date: February 12, 2004
    Inventors: Sitaram Yadavalli, Tracy Garrett Drysdale, Husnara Khan
  • Publication number: 20030084269
    Abstract: A method and apparatus for synchronizing and communicating between processing entities, such as cores or threads, in a multiprocessor. Two registers are used as a “hardware mailbox” by two processing entities of a microprocessor. A first register is used to communicate information from a first processing entity to a second processing entity, while a second register is used to communication information from the second processing entity to the first processing entity. The first and second registers are cross-decoded by the two processing entities. One or more bits in each register are used to synchronize operation of the processing entities. In a microprocessor including three or more such processing entities, a read-write register of each processing entity holds outgoing information and a read-only register of each processing entity holds incoming information. A separate logic circuit logically combines the contents of the read-write registers and stores the result in the read-only registers.
    Type: Application
    Filed: June 12, 2001
    Publication date: May 1, 2003
    Inventors: Tracy Garrett Drysdale, Scott P. Bobholz