Abstract: A time-interleaved Analog-to-Digital Converter (ADC) includes a set of time multiplexed sub-ADC circuits, each sub-ADC circuit comprising a sample-and-hold circuit. Each sample-and-hold circuit includes a bootstrap circuit for maintaining a constant voltage level between an input terminal of a switch and a gate terminal of the switch, the switch for switching between a track mode and a hold mode, and a capacitor bank associated with the bootstrap circuit such that a setting of the capacitor bank affects the voltage level.

Abstract: A time-interleaved Analog-to-Digital Converter (ADC) includes a set of time multiplexed sub-ADC circuits, each sub-ADC circuit comprising a sample-and-hold circuit. Each sample-and-hold circuit includes a bootstrap circuit for maintaining a constant voltage level between an input terminal of a switch and a gate terminal of the switch, the switch for switching between a track mode and a hold mode, and a capacitor bank associated with the bootstrap circuit such that a setting of the capacitor bank affects the voltage level.

Abstract: A reference buffer amplifier within an integrated circuit includes a first output terminal connected to a first bond pad, the first bond pad being connected to a first external pin of the integrated circuit chip, the first external pin to allow an external capacitance to be connected to the output terminal. The reference buffer further includes a variable, settable resistance sub-circuit connected to a second bond pad, the second bond pad also being connected to the first external pin. The resistance sub-circuit is configured to be set to exhibit a resistance value to critically dampen a response of the reference buffer amplifier.

Abstract: A time-interleaved Analog-to-Digital Converter (ADC) includes a set of sub-ADC circuits. Each sub-ADC circuit comprises a sample-and-hold circuit. Each sample-and-hold circuit includes a bootstrap circuit for maintaining a constant voltage level between an input terminal of a switch and a gate terminal of the switch, the switch for switching between a sample mode and a hold mode. Each sample and hold circuit also includes a capacitor bank associated with the bootstrap circuit such that a setting of the capacitor bank affects an ON state intrinsic resistance of the switch by affecting the voltage level.

Abstract: A time-interleaved Analog-to-Digital Converter (ADC) includes a set of sub-ADC circuits. Each sub-ADC circuit comprises a sample-and-hold circuit. Each sample-and-hold circuit includes a bootstrap circuit for maintaining a constant voltage level between an input terminal of a switch and a gate terminal of the switch, the switch for switching between a sample mode and a hold mode. Each sample and hold circuit also includes a capacitor bank associated with the bootstrap circuit such that a setting of the capacitor bank affects an ON state intrinsic resistance of the switch by affecting the voltage level.

Abstract: A reference buffer amplifier within an integrated circuit includes a first output terminal connected to a first bond pad, the first bond pad being connected to a first external pin of the integrated circuit chip, the first external pin to allow an external capacitance to be connected to the output terminal. The reference buffer further includes a variable, settable resistance sub-circuit connected to a second bond pad, the second bond pad also being connected to the first external pin. The resistance sub-circuit is configured to be set to exhibit a resistance value to critically dampen a response of the reference buffer amplifier.

Abstract: A track and hold circuit includes an input, a first output configured to produce a first output signal, and a second output configured to produce a second output signal while the track and hold circuit is in a first mode. While the track and hold circuit is in a second mode, the second output signal is combined with the first output signal and output on the first output.

Abstract: A pipelined Analog-to-Digital Converter (ADC) comprising a number of stages, at least one of the stages includes a sample and hold circuit. The sample and hold circuit includes a first output connected to an input of a sub-ADC, an output of the sub-ADC connected to an input of a Digital-to-Analog Converter (DAC), an output of the DAC connected to a node, and a second output connected to the node. The sample and hold circuit is configured to independently scale a signal produced by the first output and a signal produced by the second output.

Abstract: A track and hold circuit includes an input, a first output configured to produce a first output signal, and a second output configured to produce a second output signal while the track and hold circuit is in a first mode. While the track and hold circuit is in a second mode, the second output signal is combined with the first output signal and output on the first output.

Abstract: A current-mode analog-to-digital converter includes: a current input node; a current-mode sample and hold circuit configured to output a steady source of electrical current having an analog value proportional to a sampled analog value of an electrical current at the current input node; and at least one current comparator that compares the electrical current output by the current-mode sample and hold circuit to at least one reference current to produce a digital representation of the sampled analog value of the electrical current at the current input node.

Abstract: A current-mode analog-to-digital converter includes: a current input node; a current-mode sample and hold circuit configured to output a steady source of electrical current having an analog value proportional to a sampled analog value of an electrical current at the current input node; and at least one current comparator that compares the electrical current output by the current-mode sample and hold circuit to at least one reference current to produce a digital representation of the sampled analog value of the electrical current at the current input node.

Abstract: A pipelined Analog-to-Digital Converter (ADC) comprising a number of stages, at least one of the stages includes a sample and hold circuit. The sample and hold circuit includes a first output connected to an input of a sub-ADC, an output of the sub-ADC connected to an input of a Digital-to-Analog Converter (DAC), an output of the DAC connected to a node, and a second output connected to the node. The sample and hold circuit is configured to independently scale a signal produced by the first output and a signal produced by the second output.

Abstract: An imager acquires a scene's image by pixels each of which has a digital storage device which accumulates information on a pertinent portion of the image. During image acquisition, the imager moves relative to the scene, and the contents of the digital storage devices are shifted from one pixel to another. In some embodiments, less than all bits of a digital storage device are shifted, and/or the shift is accompanied by some operation on the contents of the digital storage devices. Other features are also provided.

Abstract: A light-to-frequency converter includes a switch (130) connected in series with a reverse-biased photodiode (120). A node (150) in the current path through the switch and the photodiode is connected to the input of a Schmidt trigger (160), whose output controls the switch. New techniques are provided for motion compensation, partial readouts, dark current elimination, non-destructive testing, and sensing the state of a memory cell.

Abstract: A light-to-frequency converter includes a switch (130) connected in series with a reverse-biased photodiode (120). A node (150) in the current path through the switch and the photodiode is connected to the input of a Schmidt trigger (160), whose output controls the switch. New techniques are provided for motion compensation, partial readouts, dark current elimination, non-destructive testing, and sensing the state of a memory cell.

Abstract: A light-to-frequency converter includes a switch (130) connected in series with a reverse-biased photodiode (120). A node (150) in the current path through the switch and the photodiode is connected to the input of a Schmidt trigger (160), whose output controls the switch. New techniques are provided for motion compensation, partial readouts, dark current elimination, non-destructive testing, and sensing the state of a memory cell.

Abstract: A light-to-frequency converter includes a switch (130) connected in series with a reverse-biased photodiode (120). A node (150) in the current path through the switch and the photodiode is connected to the input of a Schmidt trigger (160), whose output controls the switch. New techniques are provided for motion compensation, partial readouts, dark current elimination, non-destructive testing, and sensing the state of a memory cell.

Abstract: Systems for reducing ringing of a signal generated by a digital signal source circuit include a number of driver circuits configured to incrementally increase an output impedance of the source circuit. The increase in output impedance is configured to reduce the ringing of the signal. Methods of reducing ringing of a signal generated by a digital signal source circuit include incrementally increasing an output impedance of the source circuit. The increase in output impedance is configured to reduce the ringing of the signal.