Abstract: The application concerns prototyped custom Programmable Logic Devices (Pills) for Boolean satisfiability (SAT) problems. This approach is based on the use of clause evaluation circuits (CECs), which indicate whether or not a single variable of the clause is asserted by the clause, and variable evaluation circuits (VECs), which identify the asserted variable of a clause having exactly one variable asserted by the clause. Scaling is provided by the use of partial CEC and VEC circuits.

Abstract: A method for diagnosing bridging faults with inexpensively-obtained stuck-at signatures, in which only those faults determined to be realistic through inductive fault analysis are considered as candidates, match restrictions and match requirements are imposed during matching in order to minimize diagnosis size, and match ranking is applied and the matching criteria relaxed to further increase the effective precision and to increase the number of correct diagnoses. In addition, the method reduces the number of bridging fault candidates by constructing a dictionary of composite signatures of node pairs based on a ranking threshold.