Abstract: Systems, methods, and computer storage media for handling failures in generating structured queries from natural language queries. One of the methods includes obtaining, through a natural language front end, a natural language query from a user; converting the natural language query into structured operations to be performed on structured application programming interfaces (APIs) of a knowledge base, comprising: parsing the natural language query, analyzing the parsed query to determine dependencies, performing lexical resolution, forming a concept tree based on the dependencies and lexical resolution; analyzing the concept tree to generate a hypergraph, generate virtual query based on the hypergraph, and processing the virtual query to generate one or more structured operations; performing the one or more structured operations on the structured APIs of the knowledge base; and returning search results matching the natural language query to the user.

Abstract: A non-volatile memory device comprises an interface circuit for receiving a plurality of signals. The plurality of signals provides multiplexed address and data and command signals in a serial format. An input buffer stores a plurality of the plurality of signals received in serial format and reconstitutes the address, data and command signals, and has an output. A command circuit receives the output of the input buffer and stores the command signals therefrom. An address circuit receives the output of the input buffer and stores the address signals therefrom. A data buffer circuit receives the output of the input buffer and stores the data signals therefrom. An array of non-volatile memory cells stores data from and provides data to the data buffer in response to address signals from the address decoder. A state machine is connected to the command circuit and controls the array of non-volatile memory cells.

Abstract: A non-volatile memory device comprises an interface circuit for receiving a plurality of signals. The plurality of signals provides multiplexed address and data and command signals in a serial format. An input buffer stores a plurality of the plurality of signals received in serial format and reconstitutes the address, data and command signals, and has an output. A command circuit receives the output of the input buffer and stores the command signals therefrom. An address circuit receives the output of the input buffer and stores the address signals therefrom. A data buffer circuit receives the output of the input buffer and stores the data signals therefrom. An array of non-volatile memory cells stores data from and provides data to the data buffer in response to address signals from the address decoder. A state machine is connected to the command circuit and controls the array of non-volatile memory cells.

Abstract: A non-volatile memory device comprises an interface circuit for receiving a plurality of signals. The plurality of signals provides multiplexed address and data and command signals in a serial format. An input buffer stores a plurality of the plurality of signals received in serial format and reconstitutes the address, data and command signals, and has an output. A command circuit receives the output of the input buffer and stores the command signals therefrom. An address circuit receives the output of the input buffer and stores the address signals therefrom. A data buffer circuit receives the output of the input buffer and stores the data signals therefrom. An array of non-volatile memory cells stores data from and provides data to the data buffer in response to address signals from the address decoder. A state machine is connected to the command circuit and controls the array of non-volatile memory cells.

Abstract: A non-volatile memory device comprises an interface circuit for receiving a plurality of signals. The plurality of signals provides multiplexed address and data and command signals in a serial format. An input buffer stores a plurality of the plurality of signals received in serial format and reconstitutes the address, data and command signals, and has an output. A command circuit receives the output of the input buffer and stores the command signals therefrom. An address circuit receives the output of the input buffer and stores the address signals therefrom. A data buffer circuit receives the output of the input buffer and stores the data signals therefrom. An array of non-volatile memory cells stores data from and provides data to the data buffer in response to address signals from the address decoder. A state machine is connected to the command circuit and controls the array of non-volatile memory cells.

Abstract: A method and apparatus for scoring a data feed is provided. A feed scoring system takes as an input a data summary file produced by the data feed processing engine. The data file contains field coverage data, attribute extraction data, and mapping data. The data file is processed by the feed scoring system to create a set of scores. The scores are organized and presented in a hierarchical manner.

Abstract: A graphics system and method with which thick graphic primitives are efficiently drawn by minimizing dependence on drawing algorithms that require appreciable setup time. The method contemplates drawing a thick primitive in which an offset or displacement value is first calculated, based upon the thickness of the graphic primitive. The offset is approximately one half of the thickness of the primitive. Following calculation of the offset value, line drawing parameter values are determined for a line that is parallel to the origin line and displaced from the origin line in a minor axis direction by the displacement or offset value. A loop is then repeated for each grip point in the major axis range of the line. The loop includes an initial step in which a boundary pixel of the thick graphic primitive is drawn using the line drawing algorithm and the line drawing parameter values calculated for the offset line.

Abstract: Graphics information is efficiently transferred from a host computer to a graphics subsystem in which rendering and pixel data is generated by the host system. A masked span operation provides an assist for 3D rendering performed by the system processor of the host and other system resources. Storage of depth, alpha, stencil, and other pixel data is in system memory including one or more ancillary graphics buffers. The main processor of the host system generates pixel data associated with an image. This data is checked against the buffers. As a result of such checking, a mask is generated by the host system. The mask is transferred in burst mode across the host-graphic subsystem PCI bus to the graphics subsystem in combination with span width, and in the case of interpolated color, color base and color increment data, and X,Y coordinate of the first pixel. In the graphics subsystem the mask is employed with the other data to load the frame buffer with the portion of pixel data defined by the mask.