Abstract: Semiconductor wafers containing prime dies, knockout dies, and hybrid dies are presented. Corresponding singulated semiconductor chips containing the prime dies are also presented. The knockout dies contain a multiplicity of electrical test structures and optionally optical alignment dies. The hybrid dies may contain various combinations of electrical test structures, optical alignment structures, and serpentine shaped conductor. The serpentine shaped conductor in the hybrid die is designed to have a high confidence of overlaying at least three under bump metallization pads in the hybrid die that are oriented in the same way as at least three under bump metallization pads of a prime die. The serpentine shaped conductor is part of a two-wire Kelvin resistance scheme. A method of converting a prime die into a hybrid die includes the steps of selecting, providing, irradiating, stripping, adding, and forming.

Abstract: Method and devices to reduce integrated circuit fabrication process yield loss due to undesired interactions between PCMs and the wafer test probes during wafer sorting tests are disclosed. The described methods entail the use of a properly patterned metal layer on the PCM dies adjacent to the product dies under test. Such patterned metal layers shield traces of the wafer probes from the circuits of the PCM dies. Various exemplary metal layer patterns are also presented.

Abstract: Method and devices to reduce integrated circuit fabrication process yield loss due to undesired interactions between PCMs and the wafer test probes during wafer sorting tests are disclosed. The described methods entail the use of a properly patterned metal layer on the PCM dies adjacent to the product dies under test. Such patterned metal layers shield traces of the wafer probes from the circuits of the PCM dies. Various exemplary metal layer patterns are also presented.