Patents by Inventor Travis A. Bradfield
Travis A. Bradfield has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20130219088Abstract: Processing input/output requests may include: processing one or more input/output (IO) requests in a first IO queue associated with a first device group; detecting a queuing of one or more IO requests in a second IO queue associated with a second device group; pausing the processing one or more input/output (IO) requests in a first IO queue associated with a first device group upon a detection of a queuing of one or more IO requests in a second IO queue associated with a second device group; processing the one or more IO requests in a second IO queue associated with a second device group; and resuming the processing one or more input/output (IO) requests in a first IO queue associated with a first device group upon a completion of the processing the one or more IO requests in a second IO queue associated with a second device group.Type: ApplicationFiled: February 22, 2012Publication date: August 22, 2013Applicant: LSI CORPORATIONInventors: Lawrence J. Rawe, Gregory A. Johnson, Willliam W. Voorhees, Travis A. Bradfield, Edoardo Daelli
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Publication number: 20100124256Abstract: A method of eliminating a runaway condition in a PLL includes the steps of: determining whether the PLL is locked to an input reference signal; when the PLL is not locked to the input reference signal, determining whether a frequency of an output signal generated by the PLL exceeds a prescribed maximum frequency; and when the frequency of the output signal generated by the PLL exceeds the prescribed maximum frequency, resetting the PLL to thereby eliminate the runaway condition.Type: ApplicationFiled: November 19, 2008Publication date: May 20, 2010Inventors: Paul Jeffrey Smith, Travis A. Bradfield, Jeffrey K. Whitt
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Patent number: 7719368Abstract: A method of eliminating a runaway condition in a PLL includes the steps of: determining whether the PLL is locked to an input reference signal; when the PLL is not locked to the input reference signal, determining whether a frequency of an output signal generated by the PLL exceeds a prescribed maximum frequency; and when the frequency of the output signal generated by the PLL exceeds the prescribed maximum frequency, resetting the PLL to thereby eliminate the runaway condition.Type: GrantFiled: November 19, 2008Date of Patent: May 18, 2010Assignee: Agere Systems Inc.Inventors: Paul Jeffrey Smith, Travis A. Bradfield, Jeffrey K. Whitt
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Patent number: 7236051Abstract: An apparatus and method for filtering glitches in data signals are provided. The apparatus and method provide a programmable glitch filter that may be programmed to filter glitches of different depths. The apparatus and method further provide a glitch filter that is programmable and incorporates a synchronizer for synchronizing the filtered output from the glitch filter to a different clock domain than that of the clock input.Type: GrantFiled: March 5, 2003Date of Patent: June 26, 2007Assignee: LSI CorporationInventors: David M. Berka, Travis A. Bradfield, Tracy R. Spitler
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Patent number: 7085903Abstract: A silent mirroring protocol is provided, which eliminates the arbitration/selection times associated with all nexuses after the first nexus. During the initial SCSI bus negotiation, the initiator determines the transfer mode capability of all targets. The initiator establishes a group identification. Participants of the group recognize the group and look for an individual identification within the group. The initiator performs arbitration/selection with attention to the leader of the group. The initiator uses a message out phase with a vendor command to select a participant for a data block transfer. Each participant snoops the bus and recognizes when it is the target. If the initiator has more data to mirror, the process is repeated. When the last data block is transferred, the initiator sends a message out to the last participant, which is interpreted by the target leader as a command to release the bus. Each participant reselects the nexus initiator and returns a status.Type: GrantFiled: December 5, 2003Date of Patent: August 1, 2006Assignee: LSI CorporationInventors: Gregory A. Johnson, Travis A. Bradfield, Robert E. Ward
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Patent number: 7076577Abstract: An innovative circuit is disclosed that enhances performance on a SCSI bus by pipelining nexuses in order to associate all nexus attributes on a per nexus basis. For example, a pipeline of nexuses is created so as to associate all of the nexus attributes from different connections involved. A plurality of load stages is provided whereby each load stage can latch all nexus attributes received at that stage. The latched nexus attributes can be loaded and stored at that stage or shifted to the next stage. As a result of the loading and shifting operations, a pipeline of nexuses is created that associates all of the nexus attributes received from the different connections on a per nexus basis. Therefore, all types of data traffic can be processed concurrently on a SCSI bus, which enhances data throughput and bus performance.Type: GrantFiled: November 17, 2003Date of Patent: July 11, 2006Assignee: LSI Logic CorporationInventors: Travis A. Bradfield, Robert E. Ward, Gregory A. Johnson
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Publication number: 20060090015Abstract: A method and system for determining multi-thread direct memory activity is described. A pipelined circuit for tag availability with multi-threaded direct memory access activity may be employed. The pipelined circuit includes registers for providing a tag to a direct memory access (DMA) thread and receiving the tag upon completion of the DMA thread. The DMA engine is implemented in a multi-threaded environment allowing for out of order completion of the data transfer requests, such as an environment including a peripheral component interconnect extended (PCI-X) bus. The pipelined circuit provides a multi-threaded DMA engine with tags for transactions. In this manner, the number of DMA threads created and executed by the DMA engine may not exceed the number of stages in the pipelined circuit.Type: ApplicationFiled: October 26, 2004Publication date: April 27, 2006Inventor: Travis Bradfield
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Publication number: 20060031603Abstract: A multi-threaded DMA engine data transfer system for a data processing system and a method for transferring data in a data processing system. The DMA Engine data transfer system has at least one frame buffer for storing data transmitted or received over an interface. A multi-threaded DMA engine generates a plurality of requests to transfer data over the interface, processes the plurality of requests using the at least one frame buffer, and completes the transfer requests. The multi-threaded DMA engine data transfer system processes a plurality of data transfer requests simultaneously resulting in improved data throughput performance.Type: ApplicationFiled: August 9, 2004Publication date: February 9, 2006Inventors: Travis Bradfield, Timothy Hoglund, David Weber
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Publication number: 20050125616Abstract: A silent mirroring protocol is provided, which eliminates the arbitration/selection times associated with all nexuses after the first nexus. During the initial SCSI bus negotiation, the initiator determines the transfer mode capability of all targets. The initiator establishes a group identification. Participants of the group recognize the group and look for an individual identification within the group. The initiator performs arbitration/selection with attention to the leader of the group. The initiator uses a message out phase with a vendor command to select a participant for a data block transfer. Each participant snoops the bus and recognizes when it is the target. If the initiator has more data to mirror, the process is repeated. When the last data block is transferred, the initiator sends a message out to the last participant, which is interpreted by the target leader as a command to release the bus. Each participant reselects the nexus initiator and returns a status.Type: ApplicationFiled: December 5, 2003Publication date: June 9, 2005Inventors: Gregory Johnson, Travis Bradfield, Robert Ward
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Publication number: 20050108449Abstract: An innovative circuit is disclosed that enhances performance on a SCSI bus by pipelining nexuses in order to associate all nexus attributes on a per nexus basis. For example, a pipeline of nexuses is created so as to associate all of the nexus attributes from different connections involved. A plurality of load stages is provided whereby each load stage can latch all nexus attributes received at that stage. The latched nexus attributes can be loaded and stored at that stage or shifted to the next stage. As a result of the loading and shifting operations, a pipeline of nexuses is created that associates all of the nexus attributes received from the different connections on a per nexus basis. Therefore, all types of data traffic can be processed concurrently on a SCSI bus, which enhances data throughput and bus performance.Type: ApplicationFiled: November 17, 2003Publication date: May 19, 2005Inventors: Travis Bradfield, Robert Ward, Gregory Johnson
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Publication number: 20030137343Abstract: An apparatus and method for filtering glitches in data signals are provided. The apparatus and method provide a programmable glitch filter that may be programmed to filter glitches of different depths. The apparatus and method further provide a glitch filter that is programmable and incorporates a synchronizer for synchronizing the filtered output from the glitch filter to a different clock domain than that of the clock input.Type: ApplicationFiled: March 5, 2003Publication date: July 24, 2003Inventors: David M. Berka, Travis A. Bradfield, Tracy R. Spitler
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Patent number: 6566939Abstract: An apparatus and method for filtering glitches in data signals are provided. The apparatus and method provide a programmable glitch filter that may be programmed to filter glitches of different depths. The apparatus and method further provide a glitch filter that is programmable and incorporates a synchronizer for synchronizing the filtered output from the glitch filter to a different clock domain than that of the clock input.Type: GrantFiled: August 6, 2001Date of Patent: May 20, 2003Assignee: LSI Logic CorporationInventors: David M. Berka, Travis A. Bradfield, Tracy R. Spitler