Abstract: Encoded bitlines run globally through a memory architecture. The encoded bitlines carry an encoded representation of the data bits read from memory cells. As a specific example, the encoded representation may be carried on encoded global bitlines in an SRAM memory architecture. The encoded representation reduces power consumption when used in conjunction with bitline pre-charging or pre-discharging. The encoding technique may be implemented in circuitry other than memories and applied to any type of signal bus, e.g., for address, data, or control signals, running between any types of circuitry.

Abstract: An engine cooling system may include a housing forming an enclosed duct having an air intake opening, an air intake door, an exhaust opening, and an exhaust door; at least one heat exchanger positioned within the duct such that ambient air entering the air intake opening flows through the duct to contact the at least one heat exchanger and exits the duct through the exhaust opening; and a controller connected to vary a degree that one or both of the air intake door and exhaust door is open to modulate a mass flow rate of ambient air contacting the at least one heat exchanger to vary a heat transfer from the at least one heat exchanger to the ambient air in the duct to maintain a temperature of a fluid within the at least one heat exchanger within a preferred temperature range.

Abstract: An engine cooling system may include a housing forming an enclosed duct having an air intake opening, an air intake door, an exhaust opening, and an exhaust door; at least one heat exchanger positioned within the duct such that ambient air entering the air intake opening flows through the duct to contact the at least one heat exchanger and exits the duct through the exhaust opening; and a controller connected to vary a degree that one or both of the air intake door and exhaust door is open to modulate a mass flow rate of ambient air contacting the at least one heat exchanger to vary a heat transfer from the at least one heat exchanger to the ambient air in the duct to maintain a temperature of a fluid within the at least one heat exchanger within a preferred temperature range.

Abstract: An air charge system for an internal combustion engine may include a charge path having a charge inlet configured to receive air, and a charge outlet configured to convey air to an intake of the internal combustion engine; a first compressor in the charge path, the first compressor being driven by a motor and configured to receive the air from the charge inlet and increase temperature, pressure and volumetric flow rate of the air in the charge path; a first valve in the charge path downstream of the first compressor configured to divert at least a portion of the air leaving the first compressor from exiting the charge path through the charge outlet; and a controller configured to modulate at least one of the first valve and a speed of the motor to adjust a volumetric flow rate of air leaving the charge outlet.

Abstract: A semiconductor chip has shapes on a particular level that are small enough to require a first mask and a second mask, the first mask and the second mask used in separate exposures during processing. A circuit on the semiconductor chip requires close tracking between a first and a second FET (field effect transistor). For example, the particular level may be a gate shape level. Separate exposures of gate shapes using the first mask and the second mask will result in poorer FET tracking (e.g., gate length, threshold voltage) than for FETs having gate shapes defined by only the first mask. FET tracking is selectively improved by laying out a circuit such that selective FETs are defined by the first mask. In particular, static random access memory (SRAM) design benefits from close tracking of six or more FETs in an SRAM cell.

Abstract: A circuit and method erase at power-up all data stored in a DRAM chip for increased data security. All the DRAM memory cells are erased by turning on the transistors for the DRAM storage cells simultaneously by increasing the body voltage of cells. In the example circuit, the body voltage is increased by a charge pump controlled by a power-on-reset (POR) signal applying a voltage to the p-well of the memory cells. The added voltage to the p-well lowers the threshold voltage of the cell, such that the NFET transistor of the memory cell will turn on. With all the devices turned on, the data stored in the memory cells is erased as the voltage of all the cells connected to a common bitline coalesce to a single value.

Abstract: A method and circuit are provided for implementing smart switched decoupling capacitors to efficiently reduce power supply noise in a logic circuit, and a design structure on which the subject circuit resides. The logic circuit includes a logic macro, a high-current event control signal activating a logic function, and a switched decoupling capacitor circuit integrated within the logic macro. The switched decoupling capacitor circuit uses the high-current event control signal to control capacitor switching to discharge to a voltage supply rail responsive to activating the logic function, and to charge the capacitors.

Abstract: A circuit and method increases the repeatability of physically undetectable functions (PUFs) by enhancing the variation of signal delay through two delay chains during chip burn-in. A burn-in circuit holds the inputs of the two delay chains at opposite random values during the burn-in process. All the PFETs in the delay chains with a low value at the input will be burned in with a higher turn on voltage. Since the PFETs affected in the two delay chains are driven by opposite transitions at burn-in, alternating sets of delay components in the two delay chains are affected by the burn-in cycle. Under normal operation, both of the delay chains see the same input so only one chain has an increase in delay to achieve a statistically reliable difference in the two delay paths thereby increasing the overall repeatability of the PUF circuit.

Abstract: A circuit and method erase at power-up all data stored in a DRAM chip for increased data security. All the DRAM memory cells are erased by turning on the transistors for the DRAM storage cells simultaneously by increasing the body voltage of cells. In the example circuit, the body voltage is increased by a charge pump controlled by a power-on-reset (POR) signal applying a voltage to the p-well of the memory cells. The added voltage to the p-well lowers the threshold voltage of the cell, such that the NFET transistor of the memory cell will turn on. With all the devices turned on, the data stored in the memory cells is erased as the voltage of all the cells connected to a common bitline coalesce to a single value.

Abstract: A circuit and method increases the repeatability of physically undetectable functions (PUFs) by enhancing the variation of signal delay through two delay chains during chip burn-in. A burn-in circuit holds the inputs of the two delay chains at opposite random values during the burn-in process. All the PFETs in the delay chains with a low value at the input will be burned in with a higher turn on voltage. Since the PFETs affected in the two delay chains are driven by opposite transitions at burn-in, alternating sets of delay components in the two delay chains are affected by the burn-in cycle. Under normal operation, both of the delay chains see the same input so only one chain has an increase in delay to achieve a statistically reliable difference in the two delay paths thereby increasing the overall repeatability of the PUF circuit.

Abstract: A method and circuit are provided for implementing smart switched decoupling capacitors to efficiently reduce power supply noise in a logic circuit, and a design structure on which the subject circuit resides. The logic circuit includes a logic macro, a high-current event control signal activating a logic function, and a switched decoupling capacitor circuit integrated within the logic macro. The switched decoupling capacitor circuit uses the high-current event control signal to control capacitor switching to discharge to a voltage supply rail responsive to activating the logic function, and to charge the capacitors.

Abstract: A method and wordline voltage boosting circuit for implementing boosted wordline voltage in memories, and a design structure on which the subject circuit resides are provided. The wordline voltage boosting circuit receives a precharge signal, uses a switching transistor coupled to a bootstrap capacitor, and generates a boosted voltage level responsive to the precharge signal. The boosted voltage level is applied to a voltage supply of an output stage of a wordline driver, causing the wordline voltage level of a selected wordline to be boosted. The switching transistor is controlled by the precharge signal and a node of the bootstrap capacitor supplying the boosted voltage level is driven high by the switching transistor.

Abstract: An array built in self test (ABIST) method and circuit for implementing enhanced static random access memory (SRAM) stability and enhanced chip yield using configurable wordline voltage levels, and a design structure on which the subject circuit resides are provided. A wordline is connected to a SRAM memory cell. A plurality of wordline voltage pulldown devices is connected to the wordline. A respective wordline voltage control input signal is applied to each of the plurality of wordline voltage pulldown devices to selectively adjust the voltage level of the wordline.

Abstract: A method and circuit for implementing an enhanced dual-mode static random access memory (SRAM) performance screen ring oscillator (PSRO), and a design structure on which the subject circuit resides are provided. The dual-mode SRAM PSRO includes a plurality of SRAM base blocks connected together in a chain. Each of the plurality of SRAM base blocks includes an eight-transistor (8T) SRAM cell, a local evaluation circuit and a logic function coupled to the SRAM cell. The eight-transistor (8T) static random access memory (SRAM) cell is an unmodified 8T SRAM cell. The dual-mode SRAM PSRO includes one mode of operation, where the output frequency is determined by write-through performance of the 8T SRAM cell; and another mode of operation, where the output frequency is determined by read performance of the 8T SRAM cell.

Abstract: A design structure embodied in a machine readable medium for implementing static random access memory (SRAM) cell write performance evaluation is provided. A SRAM core includes each wordline connected to only one bit column. A ring oscillator circuit is used to generate wordline pulses. A state machine controls operations for the SRAM cell write performance evaluation circuit including the ring oscillator circuit and the SRAM core. A control signal is applied to the state machine to select a first write operation, where the circuit simultaneously writes all the cells to a known state with wide wordlines to ensure all cells are written. Then a second write operation is selected, and all the wordlines are launched simultaneously to write the cells to the opposite state. From these write operations, a required wordline pulse width to write the cell is identified.

Abstract: A method and wordline voltage boosting circuit for implementing boosted wordline voltage in memories, and a design structure on which the subject circuit resides are provided. The wordline voltage boosting circuit receives a precharge signal, uses a switching transistor coupled to a bootstrap capacitor, and generates a boosted voltage level responsive to the precharge signal. The boosted voltage level is applied to a voltage supply of an output stage of a wordline driver, causing the wordline voltage level of a selected wordline to be boosted. The switching transistor is controlled by the precharge signal and a node of the bootstrap capacitor supplying the boosted voltage level is driven high by the switching transistor.

Abstract: A SRAM cell write performance evaluation circuit includes a SRAM core where each wordline is connected to only one bit column. A ring oscillator circuit is used to generate wordline pulses. A state machine controls operations for the SRAM cell write performance evaluation circuit including the ring oscillator circuit and the SRAM core. A control signal is applied to the state machine to select a first write operation, where the circuit simultaneously writes all the cells to a known state with wide wordlines to ensure all cells are written. Then a second write operation is selected, and all the wordlines are launched simultaneously to write the cells to the opposite state. From these write operations, a required wordline pulse width to write the cell is identified.

Abstract: An array built in self test (ABIST) method and circuit for implementing enhanced static random access memory (SRAM) stability and enhanced chip yield using configurable wordline voltage levels, and a design structure on which the subject circuit resides are provided. A wordline is connected to a SRAM memory cell. A plurality of wordline voltage pulldown devices is connected to the wordline. A respective wordline voltage control input signal is applied to each of the plurality of wordline voltage pulldown devices to selectively adjust the voltage level of the wordline.

Abstract: A method and circuit for implementing an enhanced dual-mode static random access memory (SRAM) performance screen ring oscillator (PSRO), and a design structure on which the subject circuit resides are provided. The dual-mode SRAM PSRO includes a plurality of SRAM base blocks connected together in a chain. Each of the plurality of SRAM base blocks includes an eight-transistor (8T) SRAM cell, a local evaluation circuit and a logic function coupled to the SRAM cell. The eight-transistor (8T) static random access memory (SRAM) cell is an unmodified 8T SRAM cell. The dual-mode SRAM PSRO includes one mode of operation, where the output frequency is determined by write-through performance of the 8T SRAM cell; and another mode of operation, where the output frequency is determined by read performance of the 8T SRAM cell.

Abstract: Low power level shifter latch circuits with gated feedback for high speed integrated circuits, and a design structure on which the subject circuit resides are provided. A latch input stage operating in a domain of a first voltage supply receives a data input responsive to being enabled by predefined clock signals. A latch storage element coupled to the latch input stage includes a latch output stage operating in a domain of a second voltage supply provides a data output having a voltage level corresponding to the second voltage supply. The latch storage element includes a level shifting device providing level shifting from the first supply level to the second voltage supply level. The latch storage element includes feedback gate devices receiving the predefined clock signals to gate feedback to the latch input stage when data is being written to the latch input stage.