Abstract: A fence installation apparatus that is operably coupled to a vehicle wherein the vehicle is traversed along a desired fence line while the fence apparatus is utilized to provide installation of a fence. The fence installation apparatus includes a drive assembly support frame having a rear support member and front support member. The rear support member and the front support member having operably coupled thereto a first drive member and a second drive member. The first drive member and second drive member are configured to drive fence posts into the ground. The fence installation apparatus further includes a first wire dispenser that is rotatably mounted in order to provide distribution of a wire during fence installation. A second wire dispenser is further included to dispense a second wire and further has a pole mount and pole member coupled thereto for distribution of fence accessories.

Abstract: A deck extender for a personal watercraft can include a deck member supported in a cantilevered configuration over an edge of the deck of the personal watercraft. The deck extender can include mounting sleeves fixed to an upper deck of a personal watercraft with mounting tabs of the deck member received within the mounting sleeves. The deck member can include mounting mechanisms having a receptacle and a pivoting cleat mounted above the receptacle configured for mounting accessories to the deck member. The deck member can have recessed channel members for mounting accessories.

Abstract: Methods, systems, and computer programs are presented for processing Ethernet packets at a Field Programmable Gate Array (FPGA). One programmable integrated circuit includes: an internal network on chip (iNOC) comprising rows and columns; clusters, coupled to the iNOC, comprising a network access point (NAP) and programmable logic; and an Ethernet controller coupled to the iNOC. When the controller operates in packet mode, each complete inbound Ethernet packet is sent from the controller to one of the NAPs via the iNOC, where two or more NAPs are configurable to receive the complete inbound Ethernet packets from the controller. The controller is configurable to operate in quad segment interface (QSI) mode where each complete inbound Ethernet packet is broken into segments, which are sent from the controller to different NAPs via the iNOC, where two or more NAPs are configurable to receive the complete inbound Ethernet packets from the controller.

Abstract: A soil fractionation system can include a plurality of sample racks propelled by a drive system. Each sample rack can include a sample tube for holding a soil sample and a filter cup for receiving an extracted fraction of the soil sample. An extractor module of the fractionation system can include an extractor assembly and a filter assembly. A control system can control the relative positioning of the plurality of sample racks via the drive system, the relative movement between the extractor assembly and the sample tube, and the relative movement between the filter assembly and the filter cup.

Abstract: A personal watercraft with cargo-carrying surface and an anchor rail mounted on a surface of the personal watercraft. The anchor rail being adjacent to the cargo-carrying surface and exposed to an environment. The anchor rail can include an outwardly facing surface exposed to the environment, and the anchor rail is secured to the personal watercraft in such a manner that the outwardly facing surface is recessed relative to the cargo-carrying surface to form a recess or that the outwardly facing surface is flush with the cargo-carrying surface.

Abstract: Methods, systems, and computer programs are presented for processing Ethernet packets at a Field Programmable Gate Array (FPGA). One programmable integrated circuit includes: an internal network on chip (iNOC) comprising rows and columns; clusters, coupled to the iNOC, comprising a network access point (NAP) and programmable logic; and an Ethernet controller coupled to the iNOC. When the controller operates in packet mode, each complete inbound Ethernet packet is sent from the controller to one of the NAPs via the iNOC, where two or more NAPs are configurable to receive the complete inbound Ethernet packets from the controller. The controller is configurable to operate in quad segment interface (QSI) mode where each complete inbound Ethernet packet is broken into segments, which are sent from the controller to different NAPs via the iNOC, where two or more NAPs are configurable to receive the complete inbound Ethernet packets from the controller.

Abstract: A bulged, forward-acting rupture disc (10) and a pressure relief device (38) incorporating a rupture disc (10), having a line of opening (28) formed in the transition region (26) of the disc between the bulged section (12) and flange section (14) are provided. The line of opening (28) is a stress-concentrating feature that, in conjunction with a stress-intensifying edge (68) located on an associated outlet ring (42), facilitates opening of the disc (10) when exposed to a predetermined pressure acting upon the concave face (20) of the bulged section (12).

Abstract: A personal watercraft with cargo-carrying surface and an anchor rail mounted on a surface of the personal watercraft. The anchor rail being adjacent to the cargo-carrying surface and exposed to an environment. The anchor rail can include an outwardly facing surface exposed to the environment, and the anchor rail is secured to the personal watercraft in such a manner that the outwardly facing surface is recessed relative to the cargo-carrying surface to form a recess or that the outwardly facing surface is flush with the cargo-carrying surface.

Abstract: A deck extender for a personal watercraft can include a deck member supported in a cantilevered configuration over an edge of the deck of the personal watercraft. The deck extender can include mounting sleeves fixed to an upper deck of a personal watercraft with mounting tabs of the deck member received within the mounting sleeves. The deck member can include mounting mechanisms having a receptacle and a pivoting cleat mounted above the receptacle configured for mounting accessories to the deck member. The deck member can have recessed channel members for mounting accessories.

Abstract: Methods, systems, and computer programs are presented for processing Ethernet packets at a Field Programmable Gate Array (FPGA). One programmable integrated circuit includes: an internal network on chip (iNOC) comprising rows and columns; clusters, coupled to the iNOC, comprising a network access point (NAP) and programmable logic; and an Ethernet controller coupled to the iNOC. When the controller operates in packet mode, each complete inbound Ethernet packet is sent from the controller to one of the NAPs via the iNOC, where two or more NAPs are configurable to receive the complete inbound Ethernet packets from the controller. The controller is configurable to operate in quad segment interface (QSI) mode where each complete inbound Ethernet packet is broken into segments, which are sent from the controller to different NAPs via the iNOC, where two or more NAPs are configurable to receive the complete inbound Ethernet packets from the controller.

Abstract: A tile square includes a right isosceles triangular substantially rigid transparent sheet with ruler indicia adjacent to the hypotenuse and one of the equal sides. A fence is provided along the other equal side. A plurality of templates are formed in the sheet between the sides and hypotenuse. The templates include a plurality of holes for a range of pipe sizes and a series of arcs defining peripheral boundaries of a closet or toilet flange. The equal sides of the tool are at least 18 inches in length.

Abstract: Methods, systems, and computer programs are presented for processing Ethernet packets at a Field Programmable Gate Array (FPGA). One programmable integrated circuit includes: an internal network on chip (iNOC) comprising rows and columns, clusters, coupled to the iNOC, comprising a network access point (NAP) and programmable logic; and an Ethernet controller coupled to the iNOC. When the controller operates in packet mode, each complete inbound Ethernet packet is sent from the controller to one of the NAPs via the iNOC, where two or more NAPs are configurable to receive the complete inbound Ethernet packets from the controller. The controller is configurable to operate in quad segment interface (QSI) mode where each complete inbound Ethernet packet is broken into segments, which are sent from the controller to different NAPs via the iNOC, where two or more NAPs are configurable to receive the complete inbound Ethernet packets from the controller.

Abstract: A tile square includes a right isosceles triangular substantially rigid transparent sheet with ruler indicia adjacent to the hypotenuse and one of the equal sides. A fence is provided along the other equal side. A plurality of templates are formed in the sheet between the sides and hypotenuse. The templates include a plurality of holes for a range of pipe sizes and a series of arcs defining peripheral boundaries of a closet or toilet flange. The equal sides of the tool are at least 18 inches in length.

Abstract: A deck extender for a personal watercraft can include a deck member supported in a cantilevered configuration over an edge of the deck of the personal watercraft. The deck extender can include mounting sleeves fixed to an upper deck of a personal watercraft with mounting tabs of the deck member received within the mounting sleeves. The deck member can include mounting mechanisms having a receptacle and a pivoting cleat mounted above the receptacle configured for mounting accessories to the deck member. The deck member can have recessed channel members for mounting accessories.

Abstract: Methods, systems, and computer programs are presented for processing Ethernet packets at a Field Programmable Gate Array (FPGA). One programmable integrated circuit includes: an internal network on chip (iNOC) comprising rows and columns, clusters, coupled to the iNOC, comprising a network access point (NAP) and programmable logic; and an Ethernet controller coupled to the iNOC. When the controller operates in packet mode, each complete inbound Ethernet packet is sent from the controller to one of the NAPs via the iNOC, where two or more NAPs are configurable to receive the complete inbound Ethernet packets from the controller. The controller is configurable to operate in quad segment interface (QSI) mode where each complete inbound Ethernet packet is broken into segments, which are sent from the controller to different NAPs via the iNOC, where two or more NAPs are configurable to receive the complete inbound Ethernet packets from the controller.

Abstract: Methods, systems, and computer programs are presented for processing Ethernet packets at a Field Programmable Gate Array (FPGA). One programmable integrated circuit includes: an internal network on chip (iNOC) comprising rows and columns; clusters, coupled to the iNOC, comprising a network access point (NAP) and programmable logic; and an Ethernet controller coupled to the iNOC. When the controller operates in packet mode, each complete inbound Ethernet packet is sent from the controller to one of the NAPs via the iNOC, where two or more NAPs are configurable to receive the complete inbound Ethernet packets from the controller. The controller is configurable to operate in quad segment interface (QSI) mode where each complete inbound Ethernet packet is broken into segments, which are sent from the controller to different NAPs via the iNOC, where two or more NAPs are configurable to receive the complete inbound Ethernet packets from the controller.

Abstract: Methods, systems, and computer programs are presented for distributing Ethernet packets at a Field Programmable Gate Array (FPGA). One programmable integrated circuit includes: an iNOC comprising iNOC rows and iNOC columns; a set of clusters coupled to the iNOC, each cluster comprising a vertical network access point (NAP) for iNOC column communications, a horizontal NAP for iNOC row communications, a valid signal, and programmable logic, where the vertical NAP is connected to the horizontal NAP when the valid signal is activated; and an Ethernet controller coupled to the iNOC, the Ethernet controller configurable to send Ethernet-packet segments to the vertical NAPs.

Abstract: A modular lighting installation platform includes a home base unit that is configured to be used as a junction box. The home base unit includes a housing that defines a cavity. The cavity houses circuitry that configured to convert a high voltage AC input power to a low voltage DC output power. The home base unit also includes an output port that is configured to removably couple at least one of a light fixture and an accessory to the home base unit via a low voltage cable to provide the low voltage DC output power to the at least one of a light fixture and an accessory.

Abstract: Methods, systems, and computer programs are presented for distributing Ethernet packets at a Field Programmable Gate Array (FPGA). One programmable integrated circuit includes: an iNOC comprising iNOC rows and iNOC columns; a set of clusters coupled to the iNOC, each cluster comprising a vertical network access point (NAP) for iNOC column communications, a horizontal NAP for iNOC row communications, a valid signal, and programmable logic, where the vertical NAP is connected to the horizontal NAP when the valid signal is activated; and an Ethernet controller coupled to the iNOC, the Ethernet controller configurable to send Ethernet-packet segments to the vertical NAPs.

Abstract: Methods, systems, and computer programs are presented for processing Ethernet packets at a Field Programmable Gate Array (FPGA). One programmable integrated circuit includes: an internal network on chip (iNOC) comprising rows and columns; clusters, coupled to the iNOC, comprising a network access point (NAP) and programmable logic; and an Ethernet controller coupled to the iNOC. When the controller operates in packet mode, each complete inbound Ethernet packet is sent from the controller to one of the NAPs via the iNOC, where two or more NAPs are configurable to receive the complete inbound Ethernet packets from the controller. The controller is configurable to operate in quad segment interface (QSI) mode where each complete inbound Ethernet packet is broken into segments, which are sent from the controller to different NAPs via the iNOC, where two or more NAPs are configurable to receive the complete inbound Ethernet packets from the controller.