Abstract: Visible laser probing is described. In one example a probe device has a laser configured to provide a laser beam at a visible wavelength, an objective lens positioned in front of the laser to focus the laser beam on an active region of an integrated circuit through a back side of an integrated circuit die, and a detector positioned to receive a reflected laser beam reflected from the active region through a back side of the die, through the objective lens. The detector is configured to detect an amplitude modulation of the reflected laser beam wherein the amplitude modulation is attributable to the electric field at the active region.

Abstract: Visible laser probing is described. In one example a probe device has a laser configured to provide a laser beam at a visible wavelength, an objective lens positioned in front of the laser to focus the laser beam on an active region of an integrated circuit through a back side of an integrated circuit die, and a detector positioned to receive a reflected laser beam reflected from the active region through a back side of the die, through the objective lens. The detector is configured to detect an amplitude modulation of the reflected laser beam wherein the amplitude modulation is attributable to the electric field at the active region.

Abstract: An integrated circuit device having an embedded heat slug. The integrated circuit device comprises, in one embodiment, a semiconductor substrate having a frontside surface and a backside surface. The semiconductor substrate includes an integrated circuit on the frontside surface. A heat slug is disposed in an opening in the backside surface of the semiconductor substrate adjacent the integrated circuit.

Abstract: An integrated circuit device having an embedded heat slug. The integrated circuit device comprises, in one embodiment, a semiconductor substrate having a frontside surface and backside surface. The semiconductor substrate includes an integrated circuit on the frontside surface. A heat slug is disposed in an opening in the backside surface of the semiconductor substrate adjacent the integrated circuit.

Abstract: A method is provided for manufacturing a die. A supply voltage is provided to a power plane of a selected integrated circuit, formed in and on a semiconductor substrate, having a selected design, so that a respective test current flows through a plurality of test elements, of the selected integrated circuit, each being connected to a respective test point on the power plane, the test points being spaced from one another. A magnitude of each respective test current is detected. A respective test voltage is calculated at each respective test point utilizing the respective magnitude of the respective test current flowing through the respective test element connected to a respective test point. The respective test voltages are utilized to determine at which ones of the test points the respective test voltages are more than a predetermined maximum below a supply voltage.

Abstract: A method is provided for manufacturing a die. A supply voltage is provided to a power plane of a selected integrated circuit, formed in and on a semiconductor substrate, having a selected design, so that a respective test current flows through a plurality of test elements, of the selected integrated circuit, each being connected to a respective test point on the power plane, the test points being spaced from one another. A magnitude of each respective test current is detected. A respective test voltage is calculated at each respective test point utilizing the respective magnitude of the respective test current flowing through the respective test element connected to a respective test point. The respective test voltages are utilized to determine at which ones of the test points the respective test voltages are more than a predetermined maximum below a supply voltage.

Abstract: Electrostatic discharge protection circuits adapted for use in low voltage CMOS processes have at least one PFET in the primary charge conduction path, and timer circuits configured to enable the primary conduction path during ESD events and to disable the primary conduction path during steady state conditions.In a further aspect of the present invention, bias circuits for maintaining steady state gate voltages below the dielectric breakdown level are included.In a still further aspect of the present invention a bridge circuit couples a first power supply node to a second power supply node, where the second power supply node is coupled to an ESD protection circuit.