Patents by Inventor Travis Meade

Travis Meade has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240165473
    Abstract: A wobble table may be provided by a platform having a first side and a second side, opposite to the first side; a flexible rod, secured to the second side of the platform in a mounting point located at a center of gravity for the platform, wherein the flexible rod is configured to allow the platform to tilt from level; a rigid tube, coaxially surrounding at least a portion of the flexible rod, configured to constrain an amount that the flexible rod permits the platform to tilt from level; and a base from which the flexible rod and the rigid tube extend in a first direction toward the platform.
    Type: Application
    Filed: November 22, 2022
    Publication date: May 23, 2024
    Inventors: Travis Meade, Kyle Meade, Alexander Reynolds, Michael Delpapa
  • Patent number: 11704460
    Abstract: Embodiments herein provide for reverse engineering of integrated circuits (ICs) for design verification. In example embodiments, an apparatus receives a gate-level netlist for an integrated circuit (IC), generates a list of equivalence classes related to signals included in the gate-level netlist, determines control signals of the gate-level netlist based at least in part on the list of equivalence classes, determines a logic flow of a finite state transducer (FST) based at least in part on the control signals, and generates register transfer level (RTL) source code for the IC based on the FST.
    Type: Grant
    Filed: June 9, 2021
    Date of Patent: July 18, 2023
    Assignee: UNIVERSITY OF FLORIDA RESEARCH FOUNDATION, INCORPORATED
    Inventors: Yier Jin, Shaojie Zhang, James Geist, Travis Meade, Jason Liam Portillo
  • Publication number: 20210390236
    Abstract: Embodiments herein provide for reverse engineering of integrated circuits (ICs) for design verification. In example embodiments, an apparatus receives a gate-level netlist for an integrated circuit (IC), generates a list of equivalence classes related to signals included in the gate-level netlist, determines control signals of the gate-level netlist based at least in part on the list of equivalence classes, determines a logic flow of a finite state transducer (FST) based at least in part on the control signals, and generates register transfer level (RTL) source code for the IC based on the FST.
    Type: Application
    Filed: June 9, 2021
    Publication date: December 16, 2021
    Inventors: Yier Jin, Shaojie Zhang, James Geist, Travis Meade, Jason Portillo