Patents by Inventor Travis Oenning

Travis Oenning has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9401175
    Abstract: An apparatus for correcting crosstalk in an array reader magnetic recording system includes an array reader comprising a number of read heads operable to read data from a magnetic storage medium, a preamplifier configured to amplify the signals from the read heads, and a crosstalk correction circuit configured to reduce crosstalk between signals from the read heads.
    Type: Grant
    Filed: July 21, 2015
    Date of Patent: July 26, 2016
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Jaydip Bhaumik, Jeffrey A. Gleason, Scott M. O'Brien, Travis Oenning, Ross S. Wilson
  • Publication number: 20150302887
    Abstract: An apparatus for measuring cross-talk in an array reader magnetic storage system includes an array reader with multiple read heads operable to read data from a magnetic storage medium, a first preamplifier connected to a first read head, a second preamplifier connected to a second read head, and a cross-talk measurement circuit connected to the first preamplifier and to the second preamplifier, operable to measure cross-talk between a first signal from the first read head and a second signal from the second read head.
    Type: Application
    Filed: April 23, 2014
    Publication date: October 22, 2015
    Applicant: LSI Corporation
    Inventors: Travis Oenning, Ross S. Wilson, David W. Kelly, Jason S. Goldberg
  • Patent number: 9153249
    Abstract: An apparatus for measuring cross-talk in an array reader magnetic storage system includes an array reader with multiple read heads operable to read data from a magnetic storage medium, a first preamplifier connected to a first read head, a second preamplifier connected to a second read head, and a cross-talk measurement circuit connected to the first preamplifier and to the second preamplifier, operable to measure cross-talk between a first signal from the first read head and a second signal from the second read head.
    Type: Grant
    Filed: April 23, 2014
    Date of Patent: October 6, 2015
    Assignee: LSI Corporation
    Inventors: Travis Oenning, Ross S. Wilson, David W. Kelly, Jason S. Goldberg
  • Patent number: 8423873
    Abstract: Two levels of error correction decoding are performed using first and second level decoders. A composite code formed by combining an inner component code and an outer component code can be used to decode the data and correct any errors. Performing two level decoding using a composite code allows the size of the inner parity block to be reduced to a single Reed-Solomon symbol while keeping a good code rate. The first level decoder generates soft information. The soft information can indicate a most likely error event for each possible syndrome value of the inner component code. The soft information can also include error metric values for each of the most likely error events. The second level decoder generates corrected syndrome values based on the soft information using the outer component code. The most likely trellis path that corresponds to the corrected syndrome values is then selected.
    Type: Grant
    Filed: May 25, 2010
    Date of Patent: April 16, 2013
    Assignee: HGST Netherlands B.V.
    Inventors: Shaohua Yang, Richard Leo Galbraith, Ksenija Lakovic, Yuan Xing Lee, Travis Oenning, Jongseung Park, Hideki Sawaguchi, Bruce A. Wilson
  • Publication number: 20100235718
    Abstract: Two levels of error correction decoding are performed using first and second level decoders. A composite code formed by combining an inner component code and an outer component code can be used to decode the data and correct any errors. Performing two level decoding using a composite code allows the size of the inner parity block to be reduced to a single Reed-Solomon symbol while keeping a good code rate. The first level decoder generates soft information. The soft information can indicate a most likely error event for each possible syndrome value of the inner component code. The soft information can also include error metric values for each of the most likely error events. The second level decoder generates corrected syndrome values based on the soft information using the outer component code. The most likely trellis path that corresponds to the corrected syndrome values is then selected.
    Type: Application
    Filed: May 25, 2010
    Publication date: September 16, 2010
    Applicant: Hitachi Global Storage Technologies Netherlands, B.V.
    Inventors: Shaohua Yang, Richard Leo Galbraith, Ksenija Lakovic, Yuan Xing Lee, Travis Oenning, Jongseung Park, Hideki Sawaguchi, Bruce A. Wilson
  • Patent number: 7725800
    Abstract: Two levels of error correction decoding are performed using first and second level decoders. A composite code formed by combining an inner component code and an outer component code can be used to decode the data and correct any errors. Performing two level decoding using a composite code allows the size of the inner parity block to be reduced to a single Reed-Solomon symbol while keeping a good code rate. The first level decoder generates soft information. The soft information can indicate a most likely error event for each possible syndrome value of the inner component code. The soft information can also include error metric values for each of the most likely error events. The second level decoder generates corrected syndrome values based on the soft information using the outer component code. The most likely trellis path that corresponds to the corrected syndrome values is then selected.
    Type: Grant
    Filed: August 5, 2005
    Date of Patent: May 25, 2010
    Assignee: Hitachi Global Stroage Technologies Netherlands, B.V.
    Inventors: Shaohua Yang, Richard Leo Galbraith, Ksenija Lakovic, Yuan Xing Lee, Travis Oenning, Jongseung Park, Hideki Sawaguchi, Bruce A. Wilson
  • Patent number: 7590920
    Abstract: An error correction encoder inserts redundant parity information into a data stream to improve system reliability. The encoder can generate the redundant parity information using a composite code. Dummy bits are inserted into the data stream in locations reserved for parity information generated by subsequent encoding. The error correction code can have a uniform or a non-uniform span. The span corresponds to consecutive channel bits that are within a single block of a smaller parity code that is used to form a composite code. The span lengths can be variant across the whole codeword by inserting dummy bits in less than all of the spans.
    Type: Grant
    Filed: August 5, 2005
    Date of Patent: September 15, 2009
    Assignee: Hitachi Global Storage Technologies Netherlands, B.V.
    Inventors: Shaohua Yang, Mario Blaum, Richard Leo Galbraith, Ksenija Lakovic, Yuan Xing Lee, Travis Oenning, Jongseung Park, Hideki Sawaguchi
  • Patent number: 7424074
    Abstract: Embodiments of the invention provide techniques for optimizing the detector target polynomials in read/write channels to achieve the best error rate performance in recording devices. In one embodiment, a method of obtaining a detector target polynomial of a read/write channel to achieve best error rate performance in a recording device comprises: providing an initial detector target for the read/write channel; measuring a noise autocorrelation of the read/write channel at the output of equalizer using channel hardware; computing a noise autocorrelation at the output of the 1st stage target based on the measured noise autocorrelation of the read/write channel at the output of equalizer; calculating optimal coefficients for the noise whitening filter; and obtaining the optimal detector target polynomial of the read/write channel using the calculated coefficients for noise whitening filter.
    Type: Grant
    Filed: April 19, 2005
    Date of Patent: September 9, 2008
    Assignee: Hitachi Global Storage Technologies Netherlands B.V.
    Inventors: Yuan Xing Lee, Richard Leo Galbraith, Travis Oenning, Weldon Hanson
  • Publication number: 20080055125
    Abstract: A data storage system includes an encoder subsystem comprising an error correction code encoder, a modulation encoder, and a precoder, and a decoder subsystem similarly comprising a detector, an inverse precoder, a channel decoder, and an error correction code decoder. The error correction encoder applies an error correction code to the incoming user bit stream, and the modulation encoder applies so-called modulation or constrained coding to the error correction coded bit stream. The precoder applies so-called preceding to the modulation encoded bit stream. However, this preceding is applied to selected portions of the bit stream only. There can also be a permutation step where the bit sequence is permuted after the modulation encoder before preceding is applied by the precoder. The decoder subsystem operates in the inverse manner.
    Type: Application
    Filed: August 3, 2007
    Publication date: March 6, 2008
    Inventors: Roy CIDECIYAN, Ajay DHOLAKIA, Evangelos ELEFTHERIOU, Richard GALBRAITH, Weldon HANSON, Thomas MITTELHOLZER, Travis OENNING
  • Publication number: 20070044006
    Abstract: Two levels of error correction decoding are performed using first and second level decoders. A composite code formed by combining an inner component code and an outer component code can be used to decode the data and correct any errors. Performing two level decoding using a composite code allows the size of the inner parity block to be reduced to a single Reed-Solomon symbol while keeping a good code rate. The first level decoder generates soft information. The soft information can indicate a most likely error event for each possible syndrome value of the inner component code. The soft information can also include error metric values for each of the most likely error events. The second level decoder generates corrected syndrome values based on the soft information using the outer component code. The most likely trellis path that corresponds to the corrected syndrome values is then selected.
    Type: Application
    Filed: August 5, 2005
    Publication date: February 22, 2007
    Applicant: Hitachi Global Technologies Netherlands, B.V.
    Inventors: Shaohua Yang, Richard Galbraith, Ksenija Lakovic, Yuan Lee, Travis Oenning, Jongseung Park, Hideki Sawaguchi, Bruce Wilson
  • Publication number: 20070043997
    Abstract: An error correction encoder inserts redundant parity information into a data stream to improve system reliability. The encoder can generate the redundant parity information using a composite code. Dummy bits are inserted into the data stream in locations reserved for parity information generated by subsequent encoding. The error correction code can have a uniform or a non-uniform span. The span corresponds to consecutive channel bits that are within a single block of a smaller parity code that is used to form a composite code. The span lengths can be variant across the whole codeword by inserting dummy bits in less than all of the spans.
    Type: Application
    Filed: August 5, 2005
    Publication date: February 22, 2007
    Applicant: Hitachi Global Technologies Netherlands, B.V.
    Inventors: Shaohua Yang, Mario Blaum, Richard Galbraith, Ksenija Lakovic, Yuan Lee, Travis Oenning, Jongseung Park, Hideki Sawaguchi
  • Publication number: 20060235919
    Abstract: Embodiments of the invention provide techniques for optimizing the detector target polynomials in read/write channels to achieve the best error rate performance in recording devices. In one embodiment, a method of obtaining a detector target polynomial of a read/write channel to achieve best error rate performance in a recording device comprises: providing an initial detector target for the read/write channel; measuring a noise autocorrelation of the read/write channel at the output of equalizer using channel hardware; computing a noise autocorrelation at the output of the 1st stage target based on the measured noise autocorrelation of the read/write channel at the output of equalizer; calculating optimal coefficients for the noise whitening filter; and obtaining the optimal detector target polynomial of the read/write channel using the calculated coefficients for noise whitening filter.
    Type: Application
    Filed: April 19, 2005
    Publication date: October 19, 2006
    Applicant: Hitachi Global Storage Technologies Netherlands B.V.
    Inventors: Yuan Xing Lee, Richard Galbraith, Travis Oenning, Weldon Hanson
  • Publication number: 20060221478
    Abstract: A method and apparatus for providing a read channel having imbedded channel signal analysis is disclosed.
    Type: Application
    Filed: March 31, 2005
    Publication date: October 5, 2006
    Inventors: Richard Galbraith, Travis Oenning, Eric Tree, Bruce Wilson
  • Publication number: 20060195775
    Abstract: A method and apparatus for providing a read channel having combined parity and non-parity post processing is disclosed. A post-processor combines parity and non-parity post processing to make both parity and non-parity corrections so that error events that cannot be detected by parity may be corrected. Non-parity detectable error events are only kept for consideration if their likelihood is above a set threshold.
    Type: Application
    Filed: February 28, 2005
    Publication date: August 31, 2006
    Inventors: Roy Cideciyan, Ajay Dholakia, Evangelos Eleftheriou, Richard Galbraith, Weldon Hanson, Thomas Mittelholzer, Travis Oenning
  • Patent number: 7071851
    Abstract: Non-uniform modulation encoding techniques are provided to prevent data from containing bit patterns that are prone to errors during read back. Modulation encoding is performed on a data stream to remove error prone bit patterns. Unconstrained data, such as error check parity, that is inserted into the modulated data stream may contain error prone bit patterns. Stricter modulation constraints are enforced on bits that are next to the unconstrained data, than on the remaining bits. By enforcing stricter modulation constraints on these bits, an entire data bit stream can have a desired modulation constraint.
    Type: Grant
    Filed: January 31, 2005
    Date of Patent: July 4, 2006
    Assignee: Hitachi Global Storage Technologies Netherlands B.V.
    Inventors: Mario Blaum, Roy D. Cideciyan, Evangelos S. Eleftheriou, Richard Leo Galbraith, Ksenija Lakovic, Thomas Mittelholzer, Travis Oenning, Bruce A. Wilson
  • Patent number: 7064687
    Abstract: Techniques are provided for applying modulation constraints to data streams using a short block encoder. A short block encoder encodes a subset of the bits in a data stream. Then, the even and odd interleaves in a data stream are separated into two data paths. A first modulation encoder encodes the even interleave according to a first modulation constraint. A second modulation encoder encodes the odd interleave according to a second modulation constraint, which in general coincides with the modulation constraint for even interleave.
    Type: Grant
    Filed: January 31, 2005
    Date of Patent: June 20, 2006
    Assignee: Hitachi Global Storage Technologies Netherlands B.V.
    Inventors: Mario Blaum, Roy D. Cideciyan, Evangelos S. Eleftheriou, Richard Leo Galbraith, Ksenija Lakovic, Thomas Mittelholzer, Travis Oenning, Bruce A. Wilson
  • Publication number: 20060087757
    Abstract: A hard disk drive (HDD) holds data using a biphase scheme. A plurality of matched filters are used to detect binary data represented by the biphase pattern without the need for synchronous sampling or equalization.
    Type: Application
    Filed: October 27, 2004
    Publication date: April 27, 2006
    Inventors: David Flynn, Richard Galbraith, Travis Oenning
  • Patent number: 7030789
    Abstract: Techniques are provided for applying modulation constraints to data by using periodically changing symbol mappings to replace certain prohibited error prone data patterns. Initially, user data in a first base is mapped to integers of a second base using a base conversion technique. The integers in the second base correspond to symbols. Subsequently, periodically changing symbol mappings are performed during which prohibited symbols generated during base conversion are mapped to permitted symbols. The periodically changing symbol mappings occur in multiple phases, and the prohibited symbols are different in each phase. The resulting data is processed by a precoder in some embodiments.
    Type: Grant
    Filed: December 1, 2004
    Date of Patent: April 18, 2006
    Assignee: Hitachi Global Storage Technologies Netherlands B.V.
    Inventors: Roy D. Cideciyan, Evangelos S. Eleftheriou, Richard Leo Galbraith, Thomas Mittelholzer, Travis Oenning
  • Publication number: 20050213241
    Abstract: An apparatus for providing dynamic equalizer optimization is disclosed. The present invention solves the above-described problems by providing equalizer coefficient updates that converge towards the same solution as the direct method without having to first write a known pattern to the disk or requiring any prior knowledge of the data already written on the disk. The adaptive cosine function may be used to modify only a DFIR tap set, only the j and k parameters of a cosine equalizer or to modify both the tap set for a DFIR filter and the j and k parameters of the cosine equalizer. Another algorithm, such as the LMS algorithm, may be used to modify parameters not modified by the cosine algorithm.
    Type: Application
    Filed: March 25, 2004
    Publication date: September 29, 2005
    Inventors: Roy Cideciyan, Ajay Dholakia, Evangelos Eleftheriou, Richard Galbraith, Weldon Hanson, Thomas Mittelholzer, Travis Oenning, Michael Ross, David Stanek
  • Publication number: 20050138518
    Abstract: A data storage system includes an encoder subsystem comprising an error correction code encoder, a modulation encoder, and a precoder, and a decoder subsystem similarly comprising a detector, an inverse precoder, a channel decoder, and an error correction code decoder. The error correction encoder applies an error correction code to the incoming user bit stream, and the modulation encoder applies so-called modulation or constrained coding to the error correction coded bit stream. The precoder applies so-called precoding to the modulation encoded bit stream. However, this precoding is applied to selected portions of the bit stream only. There can also be a permutation step where the bit sequence is permuted after the modulation encoder before precoding is applied by the precoder. The decoder subsystem operates in the inverse manner.
    Type: Application
    Filed: December 18, 2003
    Publication date: June 23, 2005
    Inventors: Roy Cideciyan, Ajay Dholakia, Evangelos Eleftheriou, Richard Galbraith, Weldon Hanson, Thomas Mittelholzer, Travis Oenning