Patents by Inventor Travis Scheckel

Travis Scheckel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060268714
    Abstract: The management of flows can be simplified by only keeping unique flow information for locally important flows, and aggregating all other flows together. A flow control table of 16 entries, 15 unique and 1 aggregate is usually sufficient, particularly in systems where the traffic flows are relatively static. This greatly reduces the required logic for Xoff/Xon counters and timeout monitors Rather than every packet source checking each packet it sends, the flows needed by each unit are registered in the flow table and the table logic indicates to each unit whether it has any blocked flows.
    Type: Application
    Filed: May 15, 2006
    Publication date: November 30, 2006
    Inventors: Andre Szczepanek, Martin Li, Steven Marshall, Travis Scheckel
  • Publication number: 20060256879
    Abstract: High speed networking systems such as PCI-Express and Serial Rapid I/O are based on the exchange of packets across switched networks of high speed serial links. Information in the headers of these packets indicate the kind of transaction they represent. Queuing all received packets in a single queue will cause interactions between transaction types. Indirection can be used create the effect of multiple independent queues from a shared memory. This provides efficient centralized packet storage, while allowing independent processing of different transactions types.
    Type: Application
    Filed: May 15, 2006
    Publication date: November 16, 2006
    Inventors: Andre Szczepanek, Martin Li, Steven Marshall, Travis Scheckel
  • Publication number: 20060256877
    Abstract: The Rapid I/O Messaging Logical Layer relies on the receiving device to map the incoming messages into specific memory locations. This uses software programmable mapping registers. The settings are compared to the header fields of the incoming Rapid I/O messages to determine if there is a match, in which case, the packet is mapped to a queue. Accessibility to a queue through the mapping register can be limited to discrete MAILBOX/LETTER combinations, or multiple combinations based on the masking bits. Long messages may be processed through a hardware lookup table implemented to break up transactions into Rapid I/O compliant packets.
    Type: Application
    Filed: May 15, 2006
    Publication date: November 16, 2006
    Inventors: Andre Szczepanek, Martin Li, Steven Marshall, Travis Scheckel
  • Publication number: 20060256878
    Abstract: A packet transmission system based on a simple linear linked list of packet descriptors is difficult to implement with modern switch based system because transmission acknowledgments may occur out of order in relation to packet transmission. The problem lies in how packet completion is indicated to the CPU to enable for efficient packet processing. A scoreboard system is scalable to support multiple single-segment messages and multiple multi-segment messages for hundreds of packets. When a message/segment has been sent out, the context information for the packet is remembered and its key is indexed into a CAM. When segment/message response comes back, a simple hardware lookup is performed, and the associated context information is retrieved.
    Type: Application
    Filed: May 15, 2006
    Publication date: November 16, 2006
    Inventors: Andre Szczepanek, Martin Li, Steven Marshall, Travis Scheckel
  • Publication number: 20060256876
    Abstract: This invention enables many interrupt source bits spread among multiple interrupt registers. An interrupt status decode register reduces the number of read cycles required to decode the interrupt source. Each unique interrupt source has a predefined and fixed logical mapping to each bit of the decode register. The logical mapping is flexible per application. The decode register bit is set if the interrupt source is asserted and the interrupt source is mapped to that particular physical interrupt. Since each physical interrupt has an associated decode register, the ability to orthogonally arrange the sources and reduce the number of register reads is even greater.
    Type: Application
    Filed: May 15, 2006
    Publication date: November 16, 2006
    Inventors: Andre Szczepanek, Martin Li, Steven Marshall, Travis Scheckel
  • Patent number: 5401016
    Abstract: The self-contained ball-strike detector uses two transducers to detect the presence of an incoming pitch, and a series of transducers located on the upper surface of a home plate-shaped housing to determine whether the pitched ball is within the strike zone. Ultrasonic transducers are located near both the right and left boundaries of the strike zone. These transducers and a centrally-located transducer emit high frequency signals in the direction of the pitched ball. A reflected signal is used to determine whether the pitched ball is within the strike zone. The size of the strike zone may be changed to accommodate batters of different heights. The apparatus includes audio and visual indicators of whether the pitch is a "ball" or a "strike" as well as indicators if the batter is "out" or is entitled to a "walk". The apparatus maintains the ball/strike count for each batter, and has light emitting diodes to visually indicate the current count for the batter.
    Type: Grant
    Filed: May 18, 1993
    Date of Patent: March 28, 1995
    Inventors: Kenneth W. Heglund, Michael P. O'Dierno, Travis Scheckel