Patents by Inventor Travis Schluessler
Travis Schluessler has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12229870Abstract: Apparatus and method for acceleration data structure refit. For example, one embodiment of an apparatus comprises: a ray generator to generate a plurality of rays in a first graphics scene; a hierarchical acceleration data structure generator to construct an acceleration data structure comprising a plurality of hierarchically arranged nodes including inner nodes and leaf nodes stored in a memory in a depth-first search (DFS) order; traversal hardware logic to traverse one or more of the rays through the acceleration data structure; intersection hardware logic to determine intersections between the one or more rays and one or more primitives within the hierarchical acceleration data structure; a node refit unit comprising circuitry and/or logic to read consecutively through at least the inner nodes in the memory in reverse DFS order to perform a bottom-up refit operation on the hierarchical acceleration data structure.Type: GrantFiled: November 8, 2022Date of Patent: February 18, 2025Assignee: INTEL CORPORATIONInventors: Michael Apodaca, Carsten Benthin, Kai Xiao, Carson Brownlee, Timothy Rowley, Joshua Barczak, Travis Schluessler
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Patent number: 12182900Abstract: An apparatus comprising a sorting unit to sort primitives of a graphics image, the primitives to be grouped, each group to form a first level node of a hierarchical acceleration structure; a parallel reconfigurable clustering array to construct the hierarchical acceleration structure, the parallel reconfigurable clustering array comprising a plurality of processing clusters, each cluster comprising: parallel efficiency analysis circuitry to evaluate different groupings of the first level nodes for a next level of the hierarchical acceleration structure to determine efficiency values for the different groupings; and node merge circuitry to merge the first level nodes based on the efficiency values to form second level nodes.Type: GrantFiled: August 8, 2023Date of Patent: December 31, 2024Assignee: Intel CorporationInventors: Michael Doyle, Travis Schluessler, Gabor Liktor, Atsuo Kuwahara, Jefferson Amstutz
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Patent number: 12125133Abstract: Apparatus and method for speculative execution of hit and intersection shaders on programmable ray tracing architectures. For example, one embodiment of an apparatus comprises: single-instruction multiple-data (SIMD) or single-instruction multiple-thread (SIMT) execution units (EUs) to execute shaders; and ray tracing circuitry to execute a ray traversal thread, the ray tracing engine comprising: traversal/intersection circuitry, responsive to the traversal thread, to traverse a ray through an acceleration data structure comprising a plurality of hierarchically arranged nodes and to intersect the ray with a primitive contained within at least one of the nodes; and shader deferral circuitry to defer and aggregate multiple shader invocations resulting from the traversal thread until a particular triggering event is detected, wherein the multiple shaders are to be dispatched on the EUs in a single shader batch upon detection of the triggering event.Type: GrantFiled: September 22, 2023Date of Patent: October 22, 2024Assignee: Intel CorporationInventors: Gabor Liktor, Karthik Vaidyanathan, Jefferson Amstutz, Atsuo Kuwahara, Michael Doyle, Travis Schluessler
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Patent number: 12057090Abstract: Methods, systems and apparatuses may provide for technology that determines measured timing data in response to a presentation request from an application, wherein the measured timing data is associated with one or more previous frames and the presentation request is associated with one or more subsequent frames. The technology may also determine scheduling times for the subsequent frame(s) based on the measured timing data, wherein the scheduling times include a simulation time, a rendering time, a driver submission time, a hardware submission time, and a display time. In one example, the technology controls a pacing of the subsequent frame(s) on a display in accordance with the scheduling times.Type: GrantFiled: October 16, 2020Date of Patent: August 6, 2024Assignee: Intel CorporationInventors: Travis Schluessler, Thomas Petersen, Charles Moidel, Gary Smith, Zhe Wang, Rafal Rudnicki
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Publication number: 20240231851Abstract: Embodiments are generally directed to a system and method for adapting executable object to a processing unit. An embodiment of a method to adapt an executable object from a first processing unit to a second processing unit, comprises: adapting the executable object optimized for the first processing unit of a first architecture, to the second processing unit of a second architecture, wherein the second architecture is different from the first architecture, wherein the executable object is adapted to perform on the second processing unit based on a plurality of performance metrics collected while the executable object is performed on the first processing unit and the second processing unit.Type: ApplicationFiled: February 20, 2024Publication date: July 11, 2024Applicant: Intel CorporationInventors: Li Xu, Haihao Xiang, Feng Chen, Travis Schluessler, Yuheng Zhang, Sen Lin
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Patent number: 11960405Abstract: Graphics processors for implementing multi-tile memory management are disclosed. In one embodiment, a graphics processor includes a first graphics device having a local memory, a second graphics device having a local memory, and a graphics driver to provide a single virtual allocation with a common virtual address range to mirror a resource to each local memory of the first and second graphics devices.Type: GrantFiled: December 30, 2022Date of Patent: April 16, 2024Assignee: Intel CorporationInventors: Zack S. Waters, Travis Schluessler, Michael Apodaca, Ankur Shah
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Patent number: 11947977Abstract: Embodiments are generally directed to a system and method for adapting executable object to a processing unit. An embodiment of a method to adapt an executable object from a first processing unit to a second processing unit, comprises: adapting the executable object optimized for the first processing unit of a first architecture, to the second processing unit of a second architecture, wherein the second architecture is different from the first architecture, wherein the executable object is adapted to perform on the second processing unit based on a plurality of performance metrics collected while the executable object is performed on the first processing unit and the second processing unit.Type: GrantFiled: December 23, 2022Date of Patent: April 2, 2024Assignee: INTEL CORPORATIONInventors: Li Xu, Haihao Xiang, Feng Chen, Travis Schluessler, Yuheng Zhang, Sen Lin
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Publication number: 20240046403Abstract: An apparatus comprising a sorting unit to sort primitives of a graphics image, the primitives to be grouped, each group to form a first level node of a hierarchical acceleration structure; a parallel reconfigurable clustering array to construct the hierarchical acceleration structure, the parallel reconfigurable clustering array comprising a plurality of processing clusters, each cluster comprising: parallel efficiency analysis circuitry to evaluate different groupings of the first level nodes for a next level of the hierarchical acceleration structure to determine efficiency values for the different groupings; and node merge circuitry to merge the first level nodes based on the efficiency values to form second level nodes.Type: ApplicationFiled: August 8, 2023Publication date: February 8, 2024Applicant: Intel CorporationInventors: Michael DOYLE, Travis SCHLUESSLER, Gabor LIKTOR, Atsuo KUWAHARA, Jefferson AMSTUTZ
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Publication number: 20240013470Abstract: Apparatus and method for speculative execution of hit and intersection shaders on programmable ray tracing architectures. For example, one embodiment of an apparatus comprises: single-instruction multiple-data (SIMD) or single-instruction multiple-thread (SIMT) execution units (EUs) to execute shaders; and ray tracing circuitry to execute a ray traversal thread, the ray tracing engine comprising: traversal/intersection circuitry, responsive to the traversal thread, to traverse a ray through an acceleration data structure comprising a plurality of hierarchically arranged nodes and to intersect the ray with a primitive contained within at least one of the nodes; and shader deferral circuitry to defer and aggregate multiple shader invocations resulting from the traversal thread until a particular triggering event is detected, wherein the multiple shaders are to be dispatched on the EUs in a single shader batch upon detection of the triggering event.Type: ApplicationFiled: September 22, 2023Publication date: January 11, 2024Inventors: Gabor LIKTOR, Karthik VAIDYANATHAN, Jefferson AMSTUTZ, Atsuo KUWAHARA, Michael DOYLE, Travis SCHLUESSLER
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Patent number: 11769288Abstract: Apparatus and method for speculative execution of hit and intersection shaders on programmable ray tracing architectures. For example, one embodiment of an apparatus comprises: single-instruction multiple-data (SIMD) or single-instruction multiple-thread (SIMT) execution units (EUs) to execute shaders; and ray tracing circuitry to execute a ray traversal thread, the ray tracing engine comprising: traversal/intersection circuitry, responsive to the traversal thread, to traverse a ray through an acceleration data structure comprising a plurality of hierarchically arranged nodes and to intersect the ray with a primitive contained within at least one of the nodes; and shader deferral circuitry to defer and aggregate multiple shader invocations resulting from the traversal thread until a particular triggering event is detected, wherein the multiple shaders are to be dispatched on the EUs in a single shader batch upon detection of the triggering event.Type: GrantFiled: July 19, 2022Date of Patent: September 26, 2023Assignee: Intel CorporationInventors: Gabor Liktor, Karthik Vaidyanathan, Jefferson Amstutz, Atsuo Kuwahara, Michael Doyle, Travis Schluessler
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Patent number: 11763515Abstract: One embodiment provides a graphics processor comprising a hardware graphics rendering pipeline configured to perform multisample anti-aliasing, the hardware graphics rendering pipeline including pixel processing logic to determine that each sample location of a pixel of a multisample surface is associated with a clear value and resolve a color value for the pixel to a non-multisample surface via a write of metadata to indicate that the pixel has the clear value. The resolve can be a stenciled resolve that automatically bypasses execution of a pixel shader for pixels having clear color data.Type: GrantFiled: March 19, 2021Date of Patent: September 19, 2023Assignee: Intel CorporationInventors: Devan Burke, Abhishek Venkatesh, Travis Schluessler
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Patent number: 11727528Abstract: An apparatus comprising a sorting unit to sort primitives of a graphics image, the primitives to be grouped, each group to form a first level node of a hierarchical acceleration structure; a parallel reconfigurable clustering array to construct the hierarchical acceleration structure, the parallel reconfigurable clustering array comprising a plurality of processing clusters, each cluster comprising: parallel efficiency analysis circuitry to evaluate different groupings of the first level nodes for a next level of the hierarchical acceleration structure to determine efficiency values for the different groupings; and node merge circuitry to merge the first level nodes based on the efficiency values to form second level nodes.Type: GrantFiled: April 19, 2022Date of Patent: August 15, 2023Assignee: Intel CorporationInventors: Michael Doyle, Travis Schluessler, Gabor Liktor, Atsuo Kuwahara, Jefferson Amstutz
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Publication number: 20230244609Abstract: Graphics processors for implementing multi-tile memory management are disclosed. In one embodiment, a graphics processor includes a first graphics device having a local memory, a second graphics device having a local memory, and a graphics driver to provide a single virtual allocation with a common virtual address range to mirror a resource to each local memory of the first and second graphics devices.Type: ApplicationFiled: December 30, 2022Publication date: August 3, 2023Applicant: Intel CorporationInventors: ZACK S. WATERS, TRAVIS SCHLUESSLER, MICHAEL APODACA, ANKUR SHAH
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Publication number: 20230236847Abstract: Embodiments are generally directed to a system and method for adapting executable object to a processing unit. An embodiment of a method to adapt an executable object from a first processing unit to a second processing unit, comprises: adapting the executable object optimized for the first processing unit of a first architecture, to the second processing unit of a second architecture, wherein the second architecture is different from the first architecture, wherein the executable object is adapted to perform on the second processing unit based on a plurality of performance metrics collected while the executable object is performed on the first processing unit and the second processing unit.Type: ApplicationFiled: December 23, 2022Publication date: July 27, 2023Applicant: Intel CorporationInventors: Li Xu, Haihao Xiang, Feng Chen, Travis Schluessler, Yuheng Zhang, Sen Lin
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Patent number: 11710269Abstract: Position-based rendering apparatus and method for multi-die/GPU graphics processing. For example, one embodiment of a method comprises: distributing a plurality of graphics draws to a plurality of graphics processors; performing position-only shading using vertex data associated with tiles of a first draw on a first graphics processor, the first graphics processor responsively generating visibility data for each of the tiles; distributing subsets of the visibility data associated with different subsets of the tiles to different graphics processors; limiting geometry work to be performed on each tile by each graphics processor using the visibility data, each graphics processor to responsively generate rendered tiles; and wherein the rendered tiles are combined to generate a complete image frame.Type: GrantFiled: July 28, 2022Date of Patent: July 25, 2023Assignee: Intel CorporationInventors: Travis Schluessler, Zack Waters, Michael Apodaca, Daniel Johnston, Jason Surprise, Prasoonkumar Surti, Subramaniam Maiyuran, Peter Doyle, Saurabh Sharma, Ankur Shah, Murali Ramadoss
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Patent number: 11688366Abstract: Systems, methods and apparatuses may provide for technology to reduce rendering overhead associated with light field displays. The technology may conduct data formatting, re-projection, foveation, tile binning and/or image warping operations with respect to a plurality of display planes in a light field display.Type: GrantFiled: August 30, 2021Date of Patent: June 27, 2023Assignee: Intel CorporationInventors: Travis Schluessler, Abhishek Venkatesh, John Gierach, Tomer Bar-On, Devan Burke
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Publication number: 20230186545Abstract: Described herein is a cloud-based gaming system in which multiple views of a spectated E-sports event can be rendered and combined into an immersive video having at least three degrees of freedom. Low-latency generation of the immersive video is facilitated via the use of GPU-controlled non-volatile memory on which rendered data for multiple viewpoints are stored.Type: ApplicationFiled: December 15, 2021Publication date: June 15, 2023Applicant: Intel CorporationInventors: Travis Schluessler, Zack Waters, Charles Moidel, Michael Apodaca, Murali Ramadoss, Rajabali Koduri
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Publication number: 20230140640Abstract: Methods, systems and apparatuses may provide for technology that marks a graphics resource as a flush candidate during a current frame, conducts an early flush of a command buffer from the graphics resource if a write event is detected with respect to the graphics resource during a subsequent frame, and bypasses the early flush if the write event is not detected with respect to the graphics resource during the subsequent frame. In one example, the graphics resource is marked as the flush candidate in response to a read back operation of the host processor with respect to the graphics resource, wherein the read back operation retrieves a query result and/or maps a staging resource.Type: ApplicationFiled: November 3, 2021Publication date: May 4, 2023Inventors: Stav Gurtovoy, Abhishek Venkatesh, Michael Apodaca, Travis Schluessler, John Feit
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Patent number: 11580027Abstract: Graphics processors for implementing multi-tile memory management are disclosed. In one embodiment, a graphics processor includes a first graphics device having a local memory, a second graphics device having a local memory, and a graphics driver to provide a single virtual allocation with a common virtual address range to mirror a resource to each local memory of the first and second graphics devices.Type: GrantFiled: February 26, 2020Date of Patent: February 14, 2023Assignee: Intel CorporationInventors: Zack S. Waters, Travis Schluessler, Michael Apodaca, Ankur Shah
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Publication number: 20230039853Abstract: Embodiments described herein provide a graphics, media, and compute device having a tiled architecture composed of a number of tiles of smaller graphics devices. The work distribution infrastructure for such device enables the distribution of workloads across multiple tiles of the device. Work items can be submitted to any one or more of the multiple tiles, with workloads able to span multiple tiles. Additionally, upon completion of a work item, graphics, media, and/or compute engines within the device can readily acquire new work items for execution with minimal latency.Type: ApplicationFiled: October 18, 2022Publication date: February 9, 2023Applicant: Intel CorporationInventors: Balaji Vembu, Brandon Fliflet, James Valerio, Michael Apodaca, Ben Ashbaugh, Hema Nalluri, Ankur Shah, Murali Ramadoss, David Puffer, Altug Koker, Aditya Navale, Abhishek R. Appu, Joydeep Ray, Travis Schluessler