Patents by Inventor Travis T. Schluessler

Travis T. Schluessler has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • AUGMENTED REALITY VIRTUAL REALITY RAY TRACING SENSORY ENHANCEMENT SYSTEM, APPARATUS AND METHOD
    Publication number: 20190261122
    Abstract: Systems, apparatuses and methods may provide away to render augmented reality (AR) and/or virtual reality (VR) sensory enhancements using ray tracing. More particularly, systems, apparatuses and methods may provide a way to normalize environment information captured by multiple capture devices, and calculate, for an observer, the sound sources or sensed events vector paths. The systems, apparatuses and methods may detect and/or manage one or more capture devices and assign one or more the capture devices based on one or more conditions to provide observer an immersive VR/AR experience.
    Type: Application
    Filed: February 7, 2019
    Publication date: August 22, 2019
    Inventors: Joydeep Ray, Travis T. Schluessler, Prasoonkumar Surti, John H. Feit, Nikos Kaburlasos, Jacek Kwiatkowski, Abhishek R. Appu, James M. Holland, Jeffery S. Boles, Jonathan Kennedy, Louis Feng, Atsuo Kuwahara, Barnan Das, Narayan Biswal, Stanley J. Baran, Gokcen Cilingir, Nilesh V. Shah, Archie Sharma, Mayuresh M. Varerkar
  • Frequent Data Value Compression for Graphics Processing Units
    Publication number: 20190251655
    Abstract: A control surface tracks an individual cacheline in the original surface for frequent data values. If so, control surface bits are set. When reading a cacheline from memory, first the control surface bits are read. If they happen to be set, then the original memory read is skipped altogether and instead the bits from the control surface provide the value for the entire cacheline.
    Type: Application
    Filed: April 18, 2019
    Publication date: August 15, 2019
    Inventors: Saurabh Sharma, Abhishek Venkatesh, Travis T. Schluessler, Prasoonkumar Surti, Altug Koker, Aravindh V. Anantaraman, Pattabhiraman P. K., Abhishek R. Appu, Joydeep Ray, Kamal Sinha, Vasanth Ranganathan, Bhushan M. Borole, Wenyin Fu, Eric J. Hoekstra, Linda L. Hurd
  • Power management of memory chips based on working set size
    Patent number: 10365843
    Abstract: Briefly, in accordance with one or more embodiments, an apparatus comprises a memory comprising one or more physical memory chips, and a processor to implement a working set monitor to monitor a working set resident in the one or more physical memory chips. The working set monitor is to adjust a number of the physical memory chips that are powered on based on a size of the working set.
    Type: Grant
    Filed: April 10, 2017
    Date of Patent: July 30, 2019
    Assignee: Intel Corporation
    Inventors: Travis T. Schluessler, Prasoonkumar Surti, Aravindh V. Anantaraman, Abhishek R. Appu, Joydeep Ray, Altug Koker, Balaji Vembu
  • Post-packaging environment recovery of graphics on-die memory
    Patent number: 10347357
    Abstract: Systems, apparatuses and methods provide for technology that identifies a redundant portion of a packaged on-die memory and detects, during a field test of the packaged on-die memory, one or more failed cells in the packaged on-die memory. Additionally, the technology identifies whether the redundant portion includes one or more remaining memory cells, and in response to an identification that the redundant portion includes the one or more remaining memory cells, the one or more remaining memory cells in the redundant portion are substituted for the one or more failed memory cells.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: July 9, 2019
    Assignee: Intel Corporation
    Inventors: Altug Koker, Travis T. Schluessler, Ankur N. Shah, Abhishek R. Appu, Joydeep Ray, Jonathan Kennedy
  • COMPUTE OPTIMIZATION MECHANISM FOR DEEP NEURAL NETWORKS
    Publication number: 20190205736
    Abstract: An apparatus to facilitate compute optimization is disclosed. The apparatus includes a at least one processor to perform operations to implement a neural network and compute logic to accelerate neural network computations.
    Type: Application
    Filed: December 29, 2017
    Publication date: July 4, 2019
    Applicant: Intel Corporation
    Inventors: Amit Bleiweiss, Abhishek Venkatesh, Gokce Keskin, John Gierach, Oguz Elibol, Tomer Bar-On, Huma Abidi, Devan Burke, Jaikrishnan Menon, Eriko Nurvitadhi, Pruthvi Gowda Thorehosur Appajigowda, Travis T. Schluessler, Dhawal Srivastava, Nishant Patel, Anil Thomas
  • Method, apparatus, and system for energy efficiency and energy conservation including power and performance balancing between multiple processing elements and/or a communication bus
    Patent number: 10317976
    Abstract: An apparatus, method and system is described herein for efficiently balancing performance and power between processing elements based on measured workloads. If a workload of a processing element indicates that it is a bottleneck, then its performance may be increased. However, if a platform or integrated circuit including the processing element is already operating at a power or thermal limit, the increase in performance is counterbalanced by a reduction or cap in another processing elements performance to maintain compliance with the power or thermal limit. As a result, bottlenecks are identified and alleviated by balancing power allocation, even when multiple processing elements are operating at a power or thermal limit.
    Type: Grant
    Filed: June 2, 2017
    Date of Patent: June 11, 2019
    Assignee: Intel Corporation
    Inventors: Travis T. Schluessler, Russell J. Fenger
  • MOTION BIASED FOVEATED RENDERER
    Publication number: 20190147640
    Abstract: An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, a graphics subsystem communicatively coupled to the application processor, a sense engine communicatively coupled to the graphics subsystem to provide sensed information, a focus engine communicatively coupled to the sense engine and the graphics subsystem to provide focus information, a motion engine communicatively coupled to the sense engine, the focus engine, and the graphics subsystem to provide motion information, and a motion biased foveated renderer communicatively coupled to the motion engine, the focus engine, the sense engine to adjust one or more parameters of the graphics subsystem based on one or more of the sense information, the focus information, and the motion information. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: October 29, 2018
    Publication date: May 16, 2019
    Inventors: Prasoonkumar Surti, Karthik Vaidyanathan, Atsuo Kuwahara, Hugues Labbe, Sameer KP, Jonathan Kennedy, Joydeep Ray, Travis T. Schluessler, John H. Feit, Nikos Kaburlasos, Jacek Kwiatkowski, Tomer Bar-On, Carsten Benthin, Adam T. Lake, Vasanth Ranganathan, Abhishek R. Appu
  • Cloud based distributed single game calculation of shared computational work for multiple cloud gaming client devices
    Patent number: 10290141
    Abstract: Systems, apparatuses, and methods may provide for technology to process graphics data in a virtual gaming environment. The technology may identify, from graphics data in a graphics application, redundant graphics calculations relating to common frame characteristics of one or more graphical scenes to be shared between client game devices of a plurality of users and calculate, in response to the identified redundant graphics calculations, frame characteristics relating to the one or more graphical scenes. Additionally, the technology may send, over a computer network, the calculation of the frame characteristics to the client game devices.
    Type: Grant
    Filed: April 17, 2017
    Date of Patent: May 14, 2019
    Assignee: Intel Corporation
    Inventors: Jonathan Kennedy, Gabor Liktor, Jeffery S. Boles, Slawomir Grajewski, Balaji Vembu, Travis T. Schluessler, Abhishek R. Appu, Ankur N. Shah, Joydeep Ray, Altug Koker, Jacek Kwiatkowski
  • DISPLAY ENGINE SURFACE BLENDING AND ADAPTIVE TEXEL TO PIXEL RATIO SAMPLE RATE SYSTEM, APPARATUS AND METHOD
    Publication number: 20190139192
    Abstract: Systems, apparatuses and methods may provide away to blend two or more of the scene surfaces based on the focus area and an offload threshold. More particularly, systems, apparatuses and methods may provide a way to blend, by a display engine, two or more of the focus area scene surfaces and blended non-focus area scene surfaces. The systems, apparatuses and methods may include a graphics engine to render the focus area surfaces at a higher sample rate than the non-focus area scene surfaces.
    Type: Application
    Filed: September 7, 2018
    Publication date: May 9, 2019
    Inventors: Joydeep Ray, Travis T. Schluessler, John H. Feit, Nikos Kaburlasos, Jacek Kwiatkowski, Abhishek R. Appu, Balaji Vembu, Prasoonkumar Surti
  • Facilitating configuration of computing engines based on runtime workload measurements at computing devices
    Patent number: 10282804
    Abstract: A mechanism is described for facilitating configuration of computing engines based on runtime workload measurements at computing devices. A method of embodiments, as described herein, includes detecting a work unit corresponding to a workload, and collecting metrics relating to the work unit, where the metrics to indicate one or more characteristics of the work unit. The method may further include evaluating the one or more characteristics based on one or more configuration parameters relating to computing resources, and generating, based on evaluating of the one or more characteristics, a configuration plan specific to the work unit and applicable to one or more subsequent work units that are similar to the work unit. The method may further include applying and executing the configuration plan at a computing device upon execution of the one or more subsequent work units.
    Type: Grant
    Filed: June 12, 2015
    Date of Patent: May 7, 2019
    Assignee: INTEL CORPORATION
    Inventors: Travis T. Schluessler, John G. Gierach
  • Frequent data value compression for graphics processing units
    Patent number: 10262388
    Abstract: A control surface tracks an individual cacheline in the original surface for frequent data values. If so, control surface bits are set. When reading a cacheline from memory, first the control surface bits are read. If they happen to be set, then the original memory read is skipped altogether and instead the bits from the control surface provide the value for the entire cacheline.
    Type: Grant
    Filed: April 10, 2017
    Date of Patent: April 16, 2019
    Assignee: Intel Corporation
    Inventors: Saurabh Sharma, Abhishek Venkatesh, Travis T. Schluessler, Prasoonkumar Surti, Altug Koker, Aravindh V. Anantaraman, Pattabhiraman P. K., Abhishek R. Appu, Joydeep Ray, Kamal Sinha, Vasanth Ranganathan, Bhushan M. Borole, Wenyin Fu, Eric J. Hoekstra, Linda L. Hurd
  • Augmented reality virtual reality ray tracing sensory enhancement system, apparatus and method
    Patent number: 10251011
    Abstract: Systems, apparatuses and methods may provide away to render augmented reality (AR) and/or virtual reality (VR) sensory enhancements using ray tracing. More particularly, systems, apparatuses and methods may provide a way to normalize environment information captured by multiple capture devices, and calculate, for an observer, the sound sources or sensed events vector paths. The systems, apparatuses and methods may detect and/or manage one or more capture devices and assign one or more the capture devices based on one or more conditions to provide observer an immersive VR/AR experience.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: April 2, 2019
    Assignee: Intel Corporation
    Inventors: Joydeep Ray, Travis T. Schluessler, Prasoonkumar Surti, John H. Feit, Nikos Kaburlasos, Jacek Kwiatkowski, Abhishek R. Appu, James M. Holland, Jeffery S. Boles, Jonathan Kennedy, Louis Feng, Atsuo Kuwahara, Barnan Das, Narayan Biswal, Stanley J. Baran, Gokcen Cilingir, Nilesh V. Shah, Archie Sharma, Mayuresh M. Varerkar
  • Augmented reality and virtual reality feedback enhancement system, apparatus and method
    Patent number: 10242486
    Abstract: Systems, apparatuses and methods may provide away to render augmented reality and virtual reality (VR/AR) environment information. More particularly, systems, apparatuses and methods may provide a way to selectively suppress and enhance VR/AR renderings of n-dimensional environments. The systems, apparatuses and methods may deepen a user's VR/AR experience by focusing on particular feedback information, while suppressing other feedback information from the environment.
    Type: Grant
    Filed: April 17, 2017
    Date of Patent: March 26, 2019
    Assignee: Intel Corporation
    Inventors: Chandrasekaran Sakthivel, Michael Apodaca, Kai Xiao, Altug Koker, Jeffery S. Boles, Adam T. Lake, Nikos Kaburlasos, Joydeep Ray, John H. Feit, Travis T. Schluessler, Jacek Kwiatkowski, James M. Holland, Prasoonkumar Surti, Jonathan Kennedy, Louis Feng, Barnan Das, Narayan Biswal, Stanley J. Baran, Gokcen Cilingir, Nilesh V. Shah, Archie Sharma, Mayuresh M. Varerkar
  • METHOD AND APPARATUS FOR EFFICIENT PROCESSING OF DERIVED UNIFORM VALUES IN A GRAPHICS PROCESSOR
    Publication number: 20190087998
    Abstract: Various embodiments enable low frequency calculation of derived uniform values. A compiler can identify one or more portions of a shader that calculate a derived value based on an input value. For example, this portion may include instructions that use constant values, or the results of prior functions that used constant values. The constant values may include hardcoded values provided by the program (e.g., immediates) and/or other constant values. This portion of the shader can be extracted by the compiler and compiled into a first program. The compiler can compile the remainder of the shader into a second program that receives the derived uniform values from the first program. By extracting the portion(s) of the program that calculates a derived value into a separate program, the derived uniform value or values can be calculated at a lower frequency than if they were calculated for each pixel.
    Type: Application
    Filed: September 15, 2017
    Publication date: March 21, 2019
    Inventors: Travis T. SCHLUESSLER, Aleksander NEYMAN, Guei-Yuan LUEH, Thomas F. RAOUX, Bartosz SPITZBARTH
  • Multi-sample stereo renderer
    Patent number: 10235794
    Abstract: An embodiment of a parallel processor apparatus may include a sample pattern selector to select a sample pattern for a pixel, and a sample pattern subset selector communicatively coupled to the sample pattern selector to select a first subset of the sample pattern for the pixel corresponding to a left eye display frame and to select a second subset of the sample pattern for the pixel corresponding to a right eye display frame, wherein the second subset is different from the first subset. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: April 10, 2017
    Date of Patent: March 19, 2019
    Assignee: Intel Corporation
    Inventors: Nikos Kaburlasos, Joydeep Ray, John H. Feit, Travis T. Schluessler, Jacek Kwiatkowski, Philip R. Laws
  • Graphics processor with tiled compute kernels
    Patent number: 10235735
    Abstract: An embodiment of a graphics apparatus may include a tile candidate identifier to determine if a compute kernel is a tile candidate, and a compute kernel tiler communicatively coupled to the tile candidate identifier to tile the compute kernel if the compute kernel is determined to be a tile candidate. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: April 10, 2017
    Date of Patent: March 19, 2019
    Assignee: Intel Corporation
    Inventors: Abhishek Venkatesh, Prasoonkumar Surti, Slawomir Grajewski, Louis Feng, Kai Xiao, Tomasz Janczak, Devan Burke, Travis T. Schluessler
  • APPARATUS AND METHOD FOR A PROGRAMMABLE DEPTH STENCIL GRAPHICS PIPELINE STAGE
    Publication number: 20190066356
    Abstract: An apparatus and method for programmable depth stencil pipeline stage and shading. For example, one embodiment of a graphics processing apparatus comprises: a rasterizer to generate a plurality of pixel blocks, one or more of which overlap one or more primitives; programmable depth stencil circuitry to perform depth stencil tests on the pixels which overlap the one or more primitives to identify pixels which pass the depth stencil tests; and thread dispatch circuitry to dispatch pixel shader threads to perform pixel shading operations on those pixels which pass the depth stencil tests, the thread dispatch circuitry including thread dispatch recombine logic to combine pixels which have passed the depth stencil test from multiple pixel blocks into a set of pixel shader threads to be executed concurrently on single instruction multiple data (SIMD) hardware.
    Type: Application
    Filed: August 31, 2017
    Publication date: February 28, 2019
    Inventors: JOHN C. GIERACH, DARREL K. PALKE, TRAVIS T. SCHLUESSLER, PRASOONKUMAR SURTI
  • SPECIALIZED CODE PATHS IN GPU PROCESSING
    Publication number: 20190066256
    Abstract: Techniques to improve graphics processing unit (GPU) performance by introducing specialized code paths to process frequent common values are described. A shader compiler can determine instruction that, during operation, may output a common value and can introduce an enhanced shader instruction branch to process the common value to reduce overall computational requirements to execute the shader.
    Type: Application
    Filed: October 25, 2018
    Publication date: February 28, 2019
    Applicant: INTEL CORPORATION
    Inventors: SAURABH SHARMA, ABHISHEK VENKATESH, TRAVIS T. SCHLUESSLER, THOMAS F. RAOUX, RAHUL P. SATHE, JON HASSELGREN
  • METHOD AND APPARATUS FOR PROFILE-GUIDED GRAPHICS PROCESSING OPTIMIZATIONS
    Publication number: 20190066355
    Abstract: An apparatus and method for collecting and using profile data during graphics processing. For example, one embodiment of an apparatus comprises: a graphics processor to process graphics commands responsive to execution of an application; and profile storage to store graphics execution profile data associated with one or more graphics workloads; and a profile manager to read the profile data upon detecting one of the graphics workloads during execution of the application and to configure the graphics processor in accordance with the profile data.
    Type: Application
    Filed: August 31, 2017
    Publication date: February 28, 2019
    Inventors: TRAVIS T. SCHLUESSLER, MICHAEL APODACA, PENG GUO, WILLIAM B. DAVIDSON, GUEI-YUAN LUEH
  • Per-sample MSAA rendering using comprehension data
    Patent number: 10186076
    Abstract: By determining if there is redundancy between sub-samples in a multi-sampled anti-aliasing shader, determining which of at least two optimization techniques to use to reduce redundancy and eliminating a redundant shader thread using the selected technique, performance can be improved and power consumption may be reduced when sampling at the sample frequency in multi-sampled anti-aliasing.
    Type: Grant
    Filed: March 29, 2016
    Date of Patent: January 22, 2019
    Assignee: Intel Corporation
    Inventors: John G. Gierach, Travis T. Schluessler