Patents by Inventor Travis Wellington Pouarz

Travis Wellington Pouarz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of automating creation of a clock control distribution network in an integrated circuit floorplan
    Patent number: 7979838
    Abstract: The process of laying out a floorplan for a clock control distribution network in an integrated chip design is simplified and the efficiency of a staging network created is improved. Rather than manually create the staging network in HDL or as a network description table while looking at a picture of the chip floorplan in a Cadence Viewer, an automated method which runs in the Cadence environment uses an algorithmic approach to the problem of maximizing the utilization of staging latches, eliminating unnecessary power and area usage. Efficiency is maximized by updating the Physical Layout directly with the staging solution arrived at by the algorithm.
    Type: Grant
    Filed: February 15, 2008
    Date of Patent: July 12, 2011
    Assignee: International Business Machines Corporation
    Inventors: Christopher J. Berry, Jose Luis Pontes Correia Neves, Lawrence David Curley, Patrick James Meaney, Travis Wellington Pouarz, William J. Scarpero, Jr.
  • Method of Automating Creation of a Clock Control Distribution Network in an Integrated Circuit Floorplan
    Publication number: 20090210843
    Abstract: The process of laying out a floorplan for a clock control distribution network in an integrated chip design is simplified and the efficiency of a staging network created is improved. Rather than manually create the staging network in HDL or as a network description table while looking at a picture of the chip floorplan in a Cadence Viewer, an automated method which runs in the Cadence environment uses an algorithmic approach to the problem of maximizing the utilization of staging latches, eliminating unnecessary power and area usage. Efficiency is maximized by updating the Physical Layout directly with the staging solution arrived at by the algorithm.
    Type: Application
    Filed: February 15, 2008
    Publication date: August 20, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Christopher J. Berry, Jose Luis Ponters Correia Neves, Lawrence David Curley, Patrick James Meaney, Travis Wellington Pouarz, William J. Scarpero, JR.