Patents by Inventor Trefor Southwell
Trefor Southwell has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7216342Abstract: A method of linking a plurality of object files to generate an executable program, the method comprises identifying in the object files at least one routine to be locked into a cache when the program is executed, locating said routine at a set of memory addresses which man onto a set of cache locations and introducing into the executable program gaps at other sets of memory addresses which map onto the same set of cache locations.Type: GrantFiled: March 14, 2002Date of Patent: May 8, 2007Assignee: STMicroelectronics LimitedInventors: Trefor Southwell, Peter Hedinger
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Patent number: 7170512Abstract: A graphic processor having an index processing unit for pre-processing a list of vertices making up a three-dimensional image. The method of pre-processing comprising the following steps. First, decomposing the three-dimensional image into a plurality of primitive elements each defined by a set of vertices, each vertex comprising vertex information stored in a vertex storage area and addressable by a vertex index. Then receiving said vertex indices and creating a set of unique indices identifying a batch of vertices and loading only the vertices corresponding to said unique indices into the vertex storage area. Finally creating transformed primitive elements from transformed vertex information addressed in the vertex storage area using the unique indices.Type: GrantFiled: April 26, 2002Date of Patent: January 30, 2007Assignee: STMicroelectronics LimitedInventors: Trefor Southwell, Magne Sandven
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Patent number: 7062634Abstract: A processor is described in which the need to encode no-operation instructions (nops) in the program is minimised by providing a device for generating nops in response to information encoded in operative instructions.Type: GrantFiled: January 29, 2002Date of Patent: June 13, 2006Assignee: STMicroelectronics LimitedInventors: Trefor Southwell, Peter Hedinger
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Patent number: 6959363Abstract: A cache memory comprises a fetch engine arranged to issue fetch requests for accessing data items from locations in a main memory identified by access addresses in a program being executed, a pre-fetch engine controlled to issue pre-fetch requests for speculatively accessing pre-fetch data items from locations in said main memory identified by addresses which are determined as being a number of locations from respective ones of said access addresses, and a calibrator arranged to selectively vary said number of locations.Type: GrantFiled: October 22, 2002Date of Patent: October 25, 2005Assignee: STMicroelectronics LimitedInventors: Trefor Southwell, Peter Hedinger
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Patent number: 6883067Abstract: A memory map evaluation tool is provided that organizes a program in a manner most compatible with use of a cache. The tool includes a method that involves executing a first version of the program according to a first memory map to generate a program counter trace, converting the program counter trace into a specific format and then translating the program counter trace into physical addresses using a memory map to be evaluated, different from the first memory map. Those physical addresses are then used to evaluate the number of likely cache misses using a model of a direct-mapped cache for the memory map under evaluation.Type: GrantFiled: February 8, 2002Date of Patent: April 19, 2005Assignee: STMicroelectronics LimitedInventors: Trefor Southwell, Peter Hedinger, Kristen Jacobs
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Publication number: 20050013183Abstract: A method and system for validating speculative load operations. The system identifies speculative load operations that might be executed in a code sequence and after translating the virtual address of the speculative load to a physical address, a speculative load control unit is used to define a plurality of memory regions and has means for checking whether the physical addresses lie within at least one of said defined memory regions. In this way, the control unit allows the mapping of large physical page size to RAM devices and the extra address space is filtered off by the control unit so that speculative loads are not carried out in unknown regions.Type: ApplicationFiled: April 23, 2004Publication date: January 20, 2005Applicant: STMICROELECTRONICS LIMITEDInventor: Trefor Southwell
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Publication number: 20040030839Abstract: A cache memory comprises a fetch engine arranged to issue fetch requests for accessing data items from locations in a main memory identified by access addresses in a program being executed, a pre-fetch engine controlled to issue pre-fetch requests for speculatively accessing pre-fetch data items from locations in said main memory identified by addresses which are determined as being a number of locations from respective ones of said access addresses, and a calibrator arranged to selectively vary said number of locations.Type: ApplicationFiled: October 22, 2002Publication date: February 12, 2004Applicant: STMicroelectronics LimitedInventors: Trefor Southwell, Peter Hedinger
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Publication number: 20030177483Abstract: A method of linking a plurality of object files to generate an executable program, the method comprises identifying in the object files at least one routine to be locked into a cache when the program is executed, locating said routine at a set of memory addresses which man onto a set of cache locations and introducing into the executable program gaps at other sets of memory addresses which map onto the same set of cache locations.Type: ApplicationFiled: March 14, 2002Publication date: September 18, 2003Applicant: STMicroelectronics LimitedInventors: Trefor Southwell, Peter Hedinger
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Publication number: 20030154342Abstract: A memory map evaluation tool is provided which allows a program to be organised in a manner most compatible with use of a cache. This is done by executing a first version of the program according to a first memory map to generate a program counter trace, converting the program counter trace into a specific format and then translating the program counter trace into physical addresses using a memory map to be evaluated, different from the first memory map. Those physical addresses are then used to evaluate the number of likely cache misses using a model of a direct-mapped cache for the memory map under evaluation.Type: ApplicationFiled: February 8, 2002Publication date: August 14, 2003Applicant: STMicroelectronics LimitedInventors: Trefor Southwell, Peter Hedinger, Kristen Jacobs
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Publication number: 20030011592Abstract: A graphic processor having an index processing unit for pre-processing a list of vertices making up a three-dimensional image. The method of pre-processing comprising the following steps. First, decomposing the three-dimensional image into a plurality of primitive elements each defined by a set of vertices, each vertex comprising vertex information stored in a vertex storage area and addressable by a vertex index. Then receiving said vertex indices and creating a set of unique indices identifying a batch of vertices and loading only the vertices corresponding to said unique indices into the vertex storage area. Finally creating transformed primitive elements from transformed vertex information addressed in the vertex storage area using the unique indices.Type: ApplicationFiled: April 26, 2002Publication date: January 16, 2003Applicant: STMicroelectronics LimitedInventors: Trefor Southwell, Magne Sandven