Abstract: A bus switch for transferring logic signals between nodes without the problems associated with overvoltage conduction. The bus switch is an FET switch including a single primary transfer transistor. The bulk of the transfer transistor is coupled to an arbitration circuit that establishes a pseudo high-potential power rail. The pseudo high-potential rail is the highest of a potential associated with the first node, the second node, and a standard high-potential supply rail. The arbitration circuit includes regulating diode devices in parallel, one of which passes to the pseudo high-potential rail the potential associated with the first node and the other the potential associated with the second node, whichever is higher. If both are substantial equal to the potential of the standard high-potential rail, that potential is passed to the pseudo high-potential rail.

Abstract: A high-frequency switch circuit having an MOS pass gate or transfer transistor. The switch circuit of the invention includes a first impedance element coupled to the gate of the transfer transistor and, preferably, an alternative second impedance element coupled to the bulk of the transfer transistor. One or both of the impedance elements substantially negates the low-parasitic shunt capacitance associated with the transfer transistor that controls signal attenuation under high frequency operation. The impedance element is coupled in series with that parasitic capacitance to increase substantially the impedance of that pathway, thereby increasing substantially the passable bandwidth. The impedance element may simply be a resistor. The switch circuit is suitable for use in an array of applications, including signal propagation in computing systems, routers, and flat panel screen displays.

Abstract: A high-frequency switch circuit having an MOS pass gate or transfer transistor. The switch circuit of the invention includes a first impedance element coupled to the gate of the transfer transistor and, preferably, an alternative second impedance element coupled to the bulk of the transfer transistor. One or both of the impedance elements substantially negates the low-parasitic shunt capacitance associated with the transfer transistor that controls signal attenuation under high frequency operation. The impedance element is coupled in series with that parasitic capacitance to increase substantially the impedance of that pathway, thereby increasing substantially the passable bandwidth. The impedance element may simply be a resistor. The switch circuit is suitable for use in an array of applications, including signal propagation in computing systems, routers, and flat panel screen displays.

Abstract: A wave shaping circuit for shaping the transition edges of switching electrical signals. The wave shaping circuit controls voltage output as a function of time and is applicable in digital and analog systems. The shaping circuit includes one or more stages having the capability to conduct current simultaneous during signal transitions. Each simultaneous conduction current stage is coupled to a current mirror circuit powered by a power supply rail. The current mirror circuit is coupled to a capacitive element that is charged or discharged by current provided through the simultaneous conduction current stage or stages. Through selectable design of the simultaneous conduction stages, the current mirror circuit, and the capacitive element, the designer can tailor the shape of the transition curve as the input signal is propagated through the shaping circuit to the output.

Abstract: A bus switch for transferring logic signals between nodes without the problems associated with undershoot conduction. The bus switch is an FET switch including a single primary transfer transistor. The bulk of the transfer transistor is coupled to a differential logic sense circuit that is designed to establish a pseudo low-potential power rail. The logic sense circuit is coupled to the two transfer nodes and a standard low-potential power rail. It compares the potentials associated with the transfer node signals and the low-potential rail and selects the one with the lowest potential to establish the potential of the pseudo low-potential rail. The logic sense circuit provides for active selection of the lowest potential element, including under very small undershoot conditions.

Abstract: A logic level converter for translating CMOS logic signals to into differential logic signal pairs such as those associated with ECL levels. The converter includes a first converter branch coupled to the switchable CMOS level input and it provides a first switchable translated output. A second converter branch is not coupled to the input nor is it coupled to the first converter branch. The second converter branch provides a fixed reference signal output around which the output of the first converter branch switches. Changes in the input signal to the first converter branch cause its output potential to be more than or less than the potential of the fixed reference signal supplied by the second converter branch. The components of the respective branches may be tailored to position the fixed signal at a selectable level and to define the differential between the two output signals.

Abstract: A multiplexer for selecting a single output signal from a plurality of input signals. For a plurality of complementary input signal pairs in particular, the multiplexer includes for each pair of complementary input signals a control sub-circuit having a selection switch and a common resistance in parallel. The switch and the common resistance have a common low-potential node that is tied to a pair of resistances that are in parallel, wherein each of the parallel resistances is coupled to the respective high-potential nodes of a differential amplifier. A particular pair of incoming complementary input signal pairs controls the differential amplifier. An off-circuit selection signal selects which switch of a plurality of control sub-circuits is activated. When a switch is on, it creates a bypassing of the common resistance, thereby enabling the turn-on of output drivers coupled to the differential amplifier.

Abstract: A bus switch for transferring logic signals between nodes without the problems associated with undershoot conduction. The bus switch is an FET switch including a single primary transfer transistor. The bulk of the transfer transistor is coupled to a bulk regulating circuit including a pseudo low-potential power rail. The pseudo low-potential rail is coupled to one arbiter circuit associated with one of the two circuit transfer nodes and a second arbiter circuit associated with the other of the two transfer nodes. The arbiter circuits are coupled to their respective nodes or pads and to a common low-potential supply rail. The arbiter selects for coupling to the pseudo low-potential rail the signal of the lower potential between that at the pad and that of the low-potential rail. This arrangement ensures that there will be no parasitic conduction of the transfer transistor during undershoot conditions.