Patents by Inventor Trent S. Uehling
Trent S. Uehling has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9703056Abstract: A method and apparatus are provided for fabricating an electro-optical interconnect on an integrated circuit (101, 114) in which an optical circuit element (102) is formed by forming a cylinder-shaped conductive interconnect structure (120, 122, 126, 128) with one or more conductive layers formed around a central opening (129) which is located over an optically transparent layer (118) located over the optical circuit element (102).Type: GrantFiled: January 23, 2014Date of Patent: July 11, 2017Assignee: NXP USA, INC.Inventors: Sriram Neelakantan, Trent S. Uehling
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Patent number: 9659831Abstract: A method for manufacturing a semiconductor device is disclosed. The method includes generating a thermo-mechanical stress within a plurality of layers of a wafer, and after generating the thermo-mechanical stress, testing an interfacial strength level associated with one or more of the plurality of layers.Type: GrantFiled: July 25, 2014Date of Patent: May 23, 2017Assignee: NXP USA, Inc.Inventors: Trent S. Uehling, Ilko Schmadlak
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Patent number: 9548256Abstract: The present disclosure provides embodiments for a semiconductor structure including a heat spreader that includes a graphene grid having a first major surface and a second major surface opposite the first major surface. The graphene grid has a plurality of holes, each hole having a first opening in the first major surface and a second opening in the second major surface. The heat spreader also includes a first copper portion covering the first major surface of the graphene grid, a second copper portion covering the second major surface of the graphene grid, and a plurality of copper vias filling the plurality of holes.Type: GrantFiled: February 23, 2015Date of Patent: January 17, 2017Assignee: NXP USA, INC.Inventor: Trent S. Uehling
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Publication number: 20160372339Abstract: A packaged electronic device includes a package substrate, an electronic component die mounted to the package substrate, and an encapsulant bonded to a portion of the package substrate at a catechol group adhesion promoted interface that includes benzene rings bonded with the package substrate and the encapsulant.Type: ApplicationFiled: September 6, 2016Publication date: December 22, 2016Inventor: TRENT S. UEHLING
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Patent number: 9496212Abstract: By now it should be appreciated that there has been provided methods for making a packaged semiconductor device (and the resultant device) including a via layer that includes a top surface and a bottom surface; a plurality of vias within the via layer, wherein the plurality of vias extend from the bottom surface to the top surface; a first via of the plurality of vias extending from the bottom surface to the top surface at a first angle; and a second via of the plurality of vias extending from the bottom surface to the top surface at a second angle.Type: GrantFiled: December 19, 2014Date of Patent: November 15, 2016Assignee: FREESCALE SEMICONDUCTOR, INC.Inventor: Trent S. Uehling
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Patent number: 9466544Abstract: A packaged electronic device includes a package substrate, an electronic component die mounted to the package substrate, and an encapsulant bonded to a portion of the package substrate at a catechol group adhesion promoted interface that includes benzene rings bonded with the package substrate and the encapsulant.Type: GrantFiled: January 30, 2013Date of Patent: October 11, 2016Assignee: FREESCALE SEMICONDUCTOR, INC.Inventor: Trent S. Uehling
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Publication number: 20160247744Abstract: The present disclosure provides embodiments for a semiconductor structure including a heat spreader that includes a graphene grid having a first major surface and a second major surface opposite the first major surface. The graphene grid has a plurality of holes, each hole having a first opening in the first major surface and a second opening in the second major surface. The heat spreader also includes a first copper portion covering the first major surface of the graphene grid, a second copper portion covering the second major surface of the graphene grid, and a plurality of copper vias filling the plurality of holes.Type: ApplicationFiled: February 23, 2015Publication date: August 25, 2016Inventor: TRENT S. UEHLING
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Patent number: 9385064Abstract: A semiconductor structure includes a heat sink. The heat sink having a first major surface, a second major surface, a first sidewall surface, and a through-opening extending from one of the first sidewall surface or the first major surface of the heat sink to the second surface of the heat sink, and wherein the through-opening has an inflow region, a restrictive region, and an outflow region. The restrictive region is located between the inflow region and the outflow region, wherein the inflow region has an inflow surface opening at the one of the first sidewall or the first major surface, and the outflow region has an outflow surface opening at the second major surface. A cross-sectional area of the restrictive region is less than an area of the inflow surface opening and less than an area of the outflow surface opening.Type: GrantFiled: April 28, 2014Date of Patent: July 5, 2016Assignee: Freescale Semiconductor, Inc.Inventor: Trent S. Uehling
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Publication number: 20160181191Abstract: By now it should be appreciated that there has been provided methods for making a packaged semiconductor device (and the resultant device) including a via layer that includes a top surface and a bottom surface; a plurality of vias within the via layer, wherein the plurality of vias extend from the bottom surface to the top surface; a first via of the plurality of vias extending from the bottom surface to the top surface at a first angle; and a second via of the plurality of vias extending from the bottom surface to the top surface at a second angle.Type: ApplicationFiled: December 19, 2014Publication date: June 23, 2016Inventor: TRENT S. UEHLING
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Patent number: 9373539Abstract: A collapsible probe tower device and methods of forming thereof, are disclosed. In one example embodiment, a method of forming a device includes providing a semiconductor die substrate having a contact pad and a probe pad, wherein the contact pad and probe pad are adhered to the substrate, forming a contact bump by applying a conductive material to a contact structure surface of a contact tower, wherein the contact tower includes the contact pad, forming a probe bump by applying a conductive material to a probe structure surface of a probe tower, wherein the probe tower includes the probe pad, and heating the conductive material that forms the contact bump and the probe bump to provide a first reflow, wherein after the first reflow, the height of a top surface of the probe bump exceeds the height of a top surface of the contact bump.Type: GrantFiled: April 7, 2014Date of Patent: June 21, 2016Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Trent S. Uehling, Kelly F. Folts
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Patent number: 9324667Abstract: A method forms a connecting pillar to a bonding pad of an integrated circuit. A seed layer is formed over the bond pad. Photoresist is deposited over the integrated circuit. An opening is formed in the photoresist over the bond pad. The connecting pillar is formed in the opening by plating.Type: GrantFiled: January 13, 2012Date of Patent: April 26, 2016Assignee: Freescale Semiconductor, Inc.Inventors: Trent S. Uehling, Lawrence S. Klingbeil, Mostafa Vadipour, Brett P. Wilkerson, Leo M. Higgins, III
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Publication number: 20160027705Abstract: A method for manufacturing a semiconductor device is disclosed. The method includes generating a thermo-mechanical stress within a plurality of layers of a wafer, and after generating the thermo-mechanical stress, testing an interfacial strength level associated with one or more of the plurality of layers.Type: ApplicationFiled: July 25, 2014Publication date: January 28, 2016Inventors: TRENT S. UEHLING, ILKO SCHMADLAK
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Publication number: 20150311136Abstract: A semiconductor structure includes a heat sink. The heat sink having a first major surface, a second major surface, a first sidewall surface, and a through-opening extending from one of the first sidewall surface or the first major surface of the heat sink to the second surface of the heat sink, and wherein the through-opening has an inflow region, a restrictive region, and an outflow region. The restrictive region is located between the inflow region and the outflow region, wherein the inflow region has an inflow surface opening at the one of the first sidewall or the first major surface, and the outflow region has an outflow surface opening at the second major surface. A cross-sectional area of the restrictive region is less than an area of the inflow surface opening and less than an area of the outflow surface opening.Type: ApplicationFiled: April 28, 2014Publication date: October 29, 2015Inventor: TRENT S. UEHLING
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Publication number: 20150287654Abstract: A collapsible probe tower device and methods of forming thereof, are disclosed. In one example embodiment, a method of forming a device includes providing a semiconductor die substrate having a contact pad and a probe pad, wherein the contact pad and probe pad are adhered to the substrate, forming a contact bump by applying a conductive material to a contact structure surface of a contact tower, wherein the contact tower includes the contact pad, forming a probe bump by applying a conductive material to a probe structure surface of a probe tower, wherein the probe tower includes the probe pad, and heating the conductive material that forms the contact bump and the probe bump to provide a first reflow, wherein after the first reflow, the height of a top surface of the probe bump exceeds the height of a top surface of the contact bump.Type: ApplicationFiled: April 7, 2014Publication date: October 8, 2015Applicant: Freescale Semiconductor, Inc.Inventors: Trent S. Uehling, Kelly F. Folts
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Publication number: 20150205041Abstract: A method and apparatus are provided for fabricating an electro-optical interconnect on an integrated circuit (101, 114) in which an optical circuit element (102) is formed by forming a cylinder-shaped conductive interconnect structure (120, 122, 126, 128) with one or more conductive layers formed around a central opening (129) which is located over an optically transparent layer (118) located over the optical circuit element (102).Type: ApplicationFiled: January 23, 2014Publication date: July 23, 2015Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Sriram Neelakantan, Trent S. Uehling
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Patent number: 9070657Abstract: An integrated circuit package includes a substrate having a heat conducting portion integrally formed with a heat dissipating portion. First and second integrated circuit dies are mounted to opposite sides of the heat conducting portion of the substrate. The first and second integrated circuit dies may each be packaged as flip-chip configurations. Electrical connections between contact pads on the first and second integrated circuit dies may be formed through openings formed in the heat conducting portion of the substrate. The heat dissipating portion may be positioned externally from a location between the first and second integrated circuit dies so that it dissipates heat away from the integrated circuit package into the surrounding environment.Type: GrantFiled: October 8, 2013Date of Patent: June 30, 2015Assignee: Freescale Semiconductor, Inc.Inventors: Tim V. Pham, Derek S. Swanson, Trent S. Uehling
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Publication number: 20150097280Abstract: An integrated circuit package includes a substrate having a heat conducting portion integrally formed with a heat dissipating portion. First and second integrated circuit dies are mounted to opposite sides of the heat conducting portion of the substrate. The first and second integrated circuit dies may each be packaged as flip-chip configurations. Electrical connections between contact pads on the first and second integrated circuit dies may be formed through openings formed in the heat conducting portion of the substrate. The heat dissipating portion may be positioned externally from a location between the first and second integrated circuit dies so that it dissipates heat away from the integrated circuit package into the surrounding environment.Type: ApplicationFiled: October 8, 2013Publication date: April 9, 2015Inventors: Tim V. Pham, Derek S. Swanson, Trent S. Uehling
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Patent number: 8994190Abstract: A mechanism for electrically coupling a semiconductor device die to a semiconductor device package substrate that avoids introduction of excessive temperature induced stresses to the semiconductor device die interconnect is provided. In one embodiment, the semiconductor device die is mechanically attached to the package substrate (or another semiconductor device die) at room temperature through the use of a plug-in socket or wedge connection having corresponding mating features formed on the die and substrate. The mechanical interconnect features can be formed on the die and substrate interconnects using an electroplating process. The surfaces of the semiconductor device die and package substrate can then be coupled using an underfill material. A low-temperature solid state bonding process can then be used to diffuse the materials forming the plug and socket features in order to form the electrical connection.Type: GrantFiled: May 22, 2012Date of Patent: March 31, 2015Assignee: Freescale Semiconductor, Inc.Inventor: Trent S. Uehling
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Patent number: 8895409Abstract: A semiconductor wafer includes a die, an edge seal, a bond pad, a plating bus, and trace. The die is adjacent to a saw street. The edge seal is along a perimeter of the die and includes a conductive layer formed in a last interconnect layer of the die. The bond pad is formed as part of metal deposition layer above the last interconnect layer or part of the last interconnect layer. The plating bus is within the saw street. The trace is connected to the bond pad and to the plating bus (1) over the edge seal, insulated from the edge seal, and formed in the metal deposition layer or (2) through the edge seal and insulated from the edge seal.Type: GrantFiled: July 23, 2013Date of Patent: November 25, 2014Assignee: Freescale Semiconductor, Inc.Inventor: Trent S. Uehling
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Publication number: 20140210063Abstract: A packaged electronic device includes a package substrate, an electronic component die mounted to the package substrate, and an encapsulant bonded to a portion of the package substrate at a catechol group adhesion promoted interface that includes benzene rings bonded with the package substrate and the encapsulant.Type: ApplicationFiled: January 30, 2013Publication date: July 31, 2014Inventor: Trent S. Uehling