Patents by Inventor Trevor C. Meyerowitz

Trevor C. Meyerowitz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Bit masking valid sectors for write-back coalescing
    Patent number: 11609855
    Abstract: A processing device identifies a portion of data in a cache memory to be written to a managed unit of a separate memory device and determines, based on respective memory addresses, whether an additional portion of data associated with the managed unit is stored in the cache memory. The processing device further generates a bit mask identifying a first location and a second location in the managed unit, wherein the first location is associated with the portion of data and the second location is associated with the additional portion of data, and performs, based on the bit mask, a read-modify-write operation to write the portion of data to the first location in the managed unit of the separate memory device and the additional portion of data to the second location in the managed unit of the separate memory device.
    Type: Grant
    Filed: July 21, 2021
    Date of Patent: March 21, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Trevor C. Meyerowitz, Dhawal Bavishi, Fangfang Zhu
  • BIT MASKING VALID SECTORS FOR WRITE-BACK COALESCING
    Publication number: 20210357326
    Abstract: A processing device identifies a portion of data in a cache memory to be written to a managed unit of a separate memory device and determines, based on respective memory addresses, whether an additional portion of data associated with the managed unit is stored in the cache memory. The processing device further generates a bit mask identifying a first location and a second location in the managed unit, wherein the first location is associated with the portion of data and the second location is associated with the additional portion of data, and performs, based on the bit mask, a read-modify-write operation to write the portion of data to the first location in the managed unit of the separate memory device and the additional portion of data to the second location in the managed unit of the separate memory device.
    Type: Application
    Filed: July 21, 2021
    Publication date: November 18, 2021
    Inventors: Trevor C. Meyerowitz, Dhawal Bavishi, Fangfang Zhu
  • Bit masking valid sectors for write-back coalescing
    Patent number: 11099987
    Abstract: A method comprising identifying a portion of data in a first memory component to be written to a managed unit of a second memory component and determining whether an additional portion of data in the first memory component associated with the managed unit is stored at the cache memory. The method further includes generating a bit mask identifying locations of the managed unit associated with the portion of data and the additional portion of data and performing, based on the bit mask, a write operation comprising the portion of data and the additional portion of data to the managed unit of the second memory component.
    Type: Grant
    Filed: November 27, 2019
    Date of Patent: August 24, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Trevor C. Meyerowitz, Dhawal Bavishi, Fangfang Zhu
  • BIT MASKING VALID SECTORS FOR WRITE-BACK COALESCING
    Publication number: 20210157727
    Abstract: A method comprising identifying a portion of data in a first memory component to be written to a managed unit of a second memory component and determining whether an additional portion of data in the first memory component associated with the managed unit is stored at the cache memory. The method further includes generating a bit mask identifying locations of the managed unit associated with the portion of data and the additional portion of data and performing, based on the bit mask, a write operation comprising the portion of data and the additional portion of data to the managed unit of the second memory component.
    Type: Application
    Filed: November 27, 2019
    Publication date: May 27, 2021
    Inventors: Trevor C. Meyerowitz, Dhawal Bavishi, Fangfang Zhu