Patents by Inventor Trevor E. Carlson

Trevor E. Carlson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240085028
    Abstract: A cooking appliance comprises an outer frame surface defining a cooktop and the cooktop defines an outlet port. An inner frame surface defines a heating cavity disposed below the cooktop and within the outer frame surface. The inner frame surface defines an inlet port and a chimney extends between a first end connected to the inlet port and a second end connected to the outlet port for directing steam from the heating cavity outside of the cooking appliance. A nozzle apparatus is connected around the outlet port and includes an inner wall defining at least one aperture. The at least one aperture is oriented at an acute angle relative to the cooktop. The nozzle apparatus includes at least one post for connection to the cooktop.
    Type: Application
    Filed: September 9, 2022
    Publication date: March 14, 2024
    Applicant: WHIRLPOOL CORPORATION
    Inventors: Lisa E. Blumenthal, Davide Bottalico, Trevor T. Carlson, Nicholas E. Crow, Kevin Dolezan, Ankur Garg, Hemlata P. Khanvilkar, Nicholas J. Kormanik, Ajit Maruti Patil, Timothy Patrick VanAntwerp, Dustin M. Walter, Akhil Haribhau Wankhede
  • Patent number: 11010182
    Abstract: A method for simulating a set of instructions to be executed on a processor including performing a performance simulation of the processor over a number of simulation cycles. Modeling, in a frontend component, branch prediction and instruction cache is performed providing instructions to the instruction window, and modeling of an instruction window for the cycle is performed. From the simulation, a performance parameter of the processor is obtained without modeling a reorder buffer, issue queue(s), register renaming, load-store queue(s) and other buffers of the processor.
    Type: Grant
    Filed: June 17, 2013
    Date of Patent: May 18, 2021
    Assignee: UNIVERSITEIT GENT
    Inventors: Lieven Eeckhout, Stijn Eyerman, Wim Heirman, Trevor E. Carlson
  • Publication number: 20150193242
    Abstract: A method and system are described for simulating a set of instructions to be executed on a processor. The method comprises performing a performance simulation of the processor over a number of simulation cycles. Performing the performance simulation of the processor comprises modeling an instruction window for the cycle and deriving a performance parameter of the processor without modeling a reorder buffer, issue queue(s), register renaming, load-store queue(s) and other buffers of the processor.
    Type: Application
    Filed: June 17, 2013
    Publication date: July 9, 2015
    Applicant: UNIVERSITEIT GENT
    Inventors: Lieven Eeckhout, Stijn Eyerman, Wim Heirman, Trevor E. Carlson
  • Patent number: 8037116
    Abstract: A method of streamlining floating-point conversions includes determining a source coefficient and a source exponent of an input value represented by a floating-point number in a source base; estimating an approximated target exponent (ATE) using the source coefficient and the source exponent, in the event the source coefficient has a non-zero value; determining whether the ATE exceeds a maximum exponent so as to result an overflow, and outputting a predefined overflow value in the event of an overflow; determining whether the ATE exceeds a minimum exponent so as to result an underflow, and outputting a predefined underflow value in the event of an underflow; and in the event the ATE does not result in either an overflow or underflow, converting the input value to an output value represented by a converted coefficient, a converted base and the exponent of the output value.
    Type: Grant
    Filed: May 21, 2007
    Date of Patent: October 11, 2011
    Assignee: International Business Machines Corporation
    Inventors: Trevor E. Carlson, Ali Y. Duale
  • Patent number: 7873883
    Abstract: A method for scrubbing storage in a computer memory which includes a plurality of memory modules each having plurality of memory chips. The method includes selecting a pattern that correlates with physical structures for scanning the memory chips of the memory modules for errors, scanning a memory chip of a memory module for errors based upon the selected pattern. The method further includes successively scanning remaining memory chips of the respective memory module for errors when an error is found in the scanned memory chip, and scanning a memory chip of another memory module when an error is not found in the scanned memory chip of the respective memory module.
    Type: Grant
    Filed: December 19, 2007
    Date of Patent: January 18, 2011
    Assignee: International Business Machines Corporation
    Inventors: Michael E. Browne, Trevor E. Carlson, Stephanie A. Schaum, Ashwin S. Venkatraman, Maria R. Ward
  • Patent number: 7661045
    Abstract: A method and system for enterprise memory management of memory modules of a computer system. The method includes scanning memory chips of a memory module for errors, analyzing a scrub error map corresponding to a scrubbing operation of the memory module, generating a scrub map summary based upon the scrub error map analyzed, creating an error history map by adding the scrub map summary generated, analyzing the error history map created and tracking a chip location for each memory chip of the memory module including errors, and determining a scrubbing algorithm of the memory module based on the analyzed error history map. The enterprise memory management system includes a plurality of computers each including memory modules, and an enterprise memory manager which collects and analyzes error history maps corresponding to each computer and determines a scrubbing algorithm of the memory modules of each computer.
    Type: Grant
    Filed: December 19, 2007
    Date of Patent: February 9, 2010
    Assignee: International Business Machines Corporation
    Inventors: Michael E. Browne, Trevor E. Carlson, Stephanie A. Schaum, Ashwin S. Venkatraman, Maria R. Ward
  • Publication number: 20090164855
    Abstract: A method for scrubbing storage in a computer memory which includes a plurality of memory modules each having plurality of memory chips. The method includes selecting a pattern that correlates with physical structures for scanning the memory chips of the memory modules for errors, scanning a memory chip of a memory module for errors based upon the selected pattern. The method further includes successively scanning remaining memory chips of the respective memory module for errors when an error is found in the scanned memory chip, and scanning a memory chip of another memory module when an error is not found in the scanned memory chip of the respective memory module.
    Type: Application
    Filed: December 19, 2007
    Publication date: June 25, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael E. Browne, Trevor E. Carlson, Stephanie A. Schaum, Ashwin S. Venkatraman, Maria R. Ward
  • Publication number: 20090164842
    Abstract: A method and system for enterprise memory management of memory modules of a computer system. The method includes scanning memory chips of a memory module for errors, analyzing a scrub error map corresponding to a scrubbing operation of the memory module, generating a scrub map summary based upon the scrub error map analyzed, creating an error history map by adding the scrub map summary generated, analyzing the error history map created and tracking a chip location for each memory chip of the memory module including errors, and determining a scrubbing algorithm of the memory module based on the analyzed error history map. The enterprise memory management system includes a plurality of computers each including memory modules, and an enterprise memory manager which collects and analyzes error history maps corresponding to each computer and determines a scrubbing algorithm of the memory modules of each computer.
    Type: Application
    Filed: December 19, 2007
    Publication date: June 25, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael E. Browne, Trevor E. Carlson, Stephanie A. Schaum, Ashwin S. Venkatraman, Maria R. Ward
  • Patent number: 7523352
    Abstract: A system, method and computer program product for dynamically debugging a multi-node network comprising an infrastructure including a plurality of devices, each device adapted for communicating messages between nodes which may include information for synchronizing a timing clock provided in each node. The apparatus comprises a plurality of probe links interconnecting each node with a probe device that monitors data included in each message communicated by a node. Each probe device processes data from each message to determine existence of a trigger condition at a node and, in response to detecting a trigger condition, generates a specialized message for receipt by all nodes in the network. Each node responds to the specialized message by halting operation at the node and recording data useful for debugging purposes. In this manner, debug information is collected at each node at the time of a first error detection and collected dynamically at execution time without manual intervention.
    Type: Grant
    Filed: September 9, 2005
    Date of Patent: April 21, 2009
    Assignee: International Business Machines Corporation
    Inventors: Jonathan D. Bradbury, Scott M. Carlson, Trevor E. Carlson, Donald P. Crabtree, David A. Elko, Michel Henri Théodore Hack, William M. Sakal, Denise M. Sevigny, Ronald M. Smith, Sr., Li Zhang
  • Publication number: 20080263121
    Abstract: A method of performing floating-point conversions in a digital computing system includes determining a source coefficient, c1, and a source exponent, n, of an input value represented by a floating-point number in a source base, b1; converting the source coefficient to a common base, b2, and storing the converted coefficient in a first digit collection; iteratively multiplying the contents of the first digit collection by b1 and storing the intermediate results therein, wherein one or more overflow bits of the first digit collection are carried and added to one or more additional digit collections once a nonzero value is reached; and an output value in the common base is stored in the digit collections after n multiplication iterations, represented by c2×b2m, wherein c2 is the converted coefficient of the output value in the common base b2 and m is the exponent of the output value.
    Type: Application
    Filed: April 17, 2007
    Publication date: October 23, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Trevor E. Carlson, Ali Y. Duale
  • Publication number: 20080263120
    Abstract: A method of streamlining floating-point conversions includes determining a source coefficient and a source exponent of an input value represented by a floating-point number in a source base; estimating an approximated target exponent (ATE) using the source coefficient and the source exponent, in the event the source coefficient has a non-zero value; determining whether the ATE exceeds a maximum exponent so as to result an overflow, and outputting a predefined overflow value in the event of an overflow; determining whether the ATE exceeds a minimum exponent so as to result an underflow, and outputting a predefined underflow value in the event of an underflow; and in the event the ATE does not result in either an overflow or underflow, converting the input value to an output value represented by a converted coefficient, a converted base and the exponent of the output value.
    Type: Application
    Filed: May 21, 2007
    Publication date: October 23, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Trevor E. Carlson, Ali Y. Duale