Abstract: The invention is a compact sensing device that is capable of measuring the conditions (e,g, pressure, temperature) inside a cylinder of an internal combustion engine. The invention is also a cost-effective method of fabricating the sensing device. The sensing device includes a substrate, a beam, and piezo-resistive sensing elements. The beam, which is formed on the substrate, is capable of deflecting according to different pressures applied to different beam surfaces. The piezo-resistive sensing elements are coupled to the beam and detect beam deflection. The piezo-resistive sensing elements generate an electrical signal corresponding to the beam deflection.

Abstract: Multiple level logic bus drivers and receivers communicate over a bus using a multiple-level logic protocol that transfers multiple bits on each signal wire of a bus in a given interval without increasing the bus width or power dissipation. In one embodiment, four logic levels are employed using CMOS transistor circuitry operating with low voltage (e.g., 1.2V or 1.3V) power supplies (Vdd) and P and N transistor threshold voltage levels of Vtp and Vtn on the order of 0.4--0.5V. Thus, the separation between the following four logic levels is approximately uniform: Vdd; Vdd−Vtp; Vss+Vtn; and Vss. The approximately equal voltage gaps between each quantization level provide uniform noise margins for all levels. A bus noise minimization scheme and a quick recovery scheme ensure the correct data transfer in the presence of injected noise. An initial over drive feature is disclosed for shorter transition times.

Abstract: A method and apparatus are described for distributing multi-source/multi-sink control signals among nodes on a chip. Each node on the chip assists in returning the control signal to an inactive state at the start of each cycle. Thus, since all nodes contribute to returning the control signal to the inactive state, the control signal returns to the inactive state more quickly, near the start of a given cycle, and the remainder of the cycle remains available for a given node to drive the control signal. Each node includes an exemplary pulsed reset block that discharges the control signal network closest to it for a short interval, and over time the rest of the network, returning the network to an inactive state. Once the control signal network has been returned to an inactive state, the control signal may then be driven by a node during the remainder of the cycle.

Abstract: Multiple level logic bus drivers and receivers communicate over a bus using a multiple-level logic protocol that transfers multiple bits on each signal wire of a bus in a given interval without increasing the bus width or power dissipation. In one embodiment, four logic levels are employed using CMOS transistor circuitry operating with low voltage (e.g., 1.2V or 1.3V) power supplies (Vdd) and P and N transistor threshold voltage levels of Vtp and Vtnon the order of 0.4-0.5V. Thus, the separation between the following four logic levels is approximately uniform: Vdd; Vdd−Vtp; Vss+Vtn; and Vss. The approximately equal voltage gaps between each quantization level provide uniform noise margins for all levels. A bus noise minimization scheme and a quick recovery scheme ensure the correct data transfer in the presence of injected noise. An initial over drive feature is disclosed for shorter transition times.

Abstract: A method and apparatus are disclosed for transferring multi-source/multi-sink control signals using a differential signaling technique. An “active” state is transferred on a multi-source/multi-sink control signal network by inverting the previous voltage level, and an “inactive state” is transferred by maintaining the previous level. A change in the voltage level associated with a given control signal indicates that at least one node on an SoC device is asserting the corresponding control signal. In order to detect a change in the signal state from a previous cycle, each node includes a memory element, such as a latch, for maintaining the previous state. In this manner, a voltage level from the next interval can be compared to the recorded state to detect a change of state indicating an assertion of the control signal by another node.

Abstract: A method and apparatus are disclosed for transmitting multiple bits among nodes on a chip using quantized voltage levels. Multiple level logic bus drivers and receivers communicate over a bus using a multiple-level logic protocol that transfers multiple bits on each signal wire of a bus in a given interval without increasing the bus width or power dissipation. In an exemplary embodiment, four logic levels are employed using CMOS transistor circuitry operating with low voltage (e.g., 1.2V or 1.3V) power supplies (Vdd) and P and N transistor threshold voltage levels of Vtp and Vtn on the order of 0.4−0.5V. Thus, the separation between the following four logic levels is approximately uniform: Vdd; Vdd−Vtp; Vss+Vtn; and Vss. The approximately equal voltage gaps between each quantization level provide uniform noise margins for all levels. In addition, since the absolute magnitude of the coupling noise is much lower, it requires less active power to recover from an AC injected noise source.

Abstract: A method and apparatus are disclosed for distributing multi-source/multi-sink control signals among a number of nodes on a chip. Each node on the chip assists in returning the control signal to an inactive state at the start of each cycle. Thus, since all nodes contribute to returning the control signal to the inactive state, the control signal returns to the inactive state more quickly, near the start of a given cycle, and the remainder of the cycle remains available for a given node to drive the control signal. Each node on the chip includes an exemplary pulsed reset block that discharges the control signal network closest to it for a short interval, and over time the rest of the network, returning the network to an inactive state. Once the control signal network has been returned to an inactive state, the control signal may then be driven by a node during the remainder of the cycle.

Abstract: Interface apparatus for connection between a data handling device and a data communication medium to enable data to be transferred between the device and the medium, is constituted, inter alia, by a data alignment device (7, 8) coupled in use to the data handling device. A memory (5, 6) is coupled for data transfer to the data alignment device (7, 8) and includes a number of substantially identical subsidiary, First-In-First-Out (FIFO) memories arranged in parallel. The number of subsidiary memories is chosen such that their overall width is at least equal to the longest length of data to be transferred between the memory (5, 6) and the alignment device (7, 8) in a single transfer step and the width of each subsidiary memory is equal to the shortest length of data to be transferred between the memory and the alignment device in a single transfer step.

Abstract: The present invention minimizes unneeded memory accesses by providing a digital processor having control circuit for terminating on-going memory accesses, and by a data transfer circuit that allow jump instructions to be detected sooner in the decode unit. The digital processor includes a decode unit, fetch unit and a memory controller. When the decode unit of the present invention processor determines that a discontinuity must occur in the instruction fetch sequence, it asserts a "jump taken" signal to the fetch unit to indicate that any pre-fetched instruction codes are to be discarded and that fetching is to resume at a new fetch program counter (FPC) value. If the fetch unit is currently stalled because of an outstanding request to the memory controller unit, then the fetch unit asserts an "abort" signal to the memory controller.

Abstract: A technique for configuring a processor allows the processor to interface with external buses of different types; for example, busses having different data widths. Configuration data is stored in a memory, typically a read-only memory, and transferred to the processor during a system configuration period. An initial configuration fetch may be accomplished to retrieve the configuration information prior to executing an actual processor instruction. Alternatively, the configuration information may be included in an actual instruction word. The system configuration period typically occurs during the initial power-on sequence, but may occur at other times.