Abstract: Hardware assisted high speed serial (HSS) transceiver testing including receiving, by a link layer hardware state machine on a HSS transmitting device, an instruction to generate a test pattern, wherein the test pattern comprises a sequence of data units; loading, by the link layer hardware state machine, each unique data unit into embedded random access memory (RAM); generating, by the link layer hardware state machine, the test pattern comprising the sequence of data units using the unique data units stored in the embedded RAM, wherein at least one of the unique data units is repeated in the sequence of data units of the test pattern; and sending, by the link layer hardware state machine, the generated test pattern to an input of a HSS transceiver.

Abstract: Hardware error detection on a high-speed serial (HSS) connection including tracking, by a hardware state machine on a HSS receiver, errors in a data stream, wherein tracking, by the hardware state machine, the errors in the data stream comprises, for each sample of incoming data: inspecting, by the hardware state machine, a detected error indicator in a test control register to determine whether an error has been detected in the sample; incrementing, by the hardware state machine, an error count in a hardware error counter if the test control register indicates an error has been detected in the sample; clearing, by the hardware state machine, the detected error indicator if the test control register indicates an error has been detected in the sample; and incrementing, by the hardware state machine, a sample count in a sample count register.

Abstract: Hardware assisted high speed serial (HSS) transceiver testing including receiving, by a link layer hardware state machine on a HSS transmitting device, an instruction to generate a test pattern, wherein the test pattern comprises a sequence of data units; loading, by the link layer hardware state machine, each unique data unit into embedded random access memory (RAM); generating, by the link layer hardware state machine, the test pattern comprising the sequence of data units using the unique data units stored in the embedded RAM, wherein at least one of the unique data units is repeated in the sequence of data units of the test pattern; and sending, by the link layer hardware state machine, the generated test pattern to an input of a HSS transceiver.

Abstract: Hardware error detection on a high-speed serial (HSS) connection including tracking, by a hardware state machine on a HSS receiver, errors in a data stream, wherein tracking, by the hardware state machine, the errors in the data stream comprises, for each sample of incoming data: inspecting, by the hardware state machine, a detected error indicator in a test control register to determine whether an error has been detected in the sample; incrementing, by the hardware state machine, an error count in a hardware error counter if the test control register indicates an error has been detected in the sample; clearing, by the hardware state machine, the detected error indicator if the test control register indicates an error has been detected in the sample; and incrementing, by the hardware state machine, a sample count in a sample count register.

Abstract: A semiconductor wafer comprises a first chip and a second chip, each chip comprising a core, link layer and physical layer. A kerf area physically connects the two chips on the wafer, and a kerf area interconnect selectively couples the link layers of the two chips while the two physical layers are disabled.

Abstract: A method for calibrating resistors on an integrated circuit chip via a daisy chain scheme. The method comprises the step of configuring one or more links of the daisy chain scheme, wherein each of the one or more links comprises one or more master resistors and one or more slave resistors. The method further comprises the steps of calibrating at least one on-chip reference resistor, the one or more master resistors, and the one or more slave resistors via the daisy chain scheme. The method using the daisy chain scheme enables resistance of at least one off-chip reference resistor to be duplicated to multiple distant locations while maintaining a low mismatch error.

Abstract: A method, system and computer program product for preventing execution of pirated software. A file is loaded on an end user's computer containing a binary image that is generated by removing one or more code bits from an executable code. A request is sent to a remote server to return a software key required for execution of the executable code from the binary image. The software key is downloaded to the end user's computer on which the binary image is loaded. One or more bits from the software key is inserted into the appropriate location of the binary image to regenerate the executable code. The executable code is enabled for execution on the end user's computer only following the embedding of the one or more bits.

Abstract: A structure and method for fabricating a light emitting diode and a light detecting diode on a silicon-on-insulator (SOI) wafer is provided. Specifically, the structure and method involves forming a light emitting diode and light detecting diode on the SOI wafer's backside and utilizing a deep trench formed in the wafer as an alignment marker. The alignment marker can be detected by x-ray diffraction, reflectivity, or diffraction grating techniques. Moreover, the alignment marker can be utilized to pattern openings and perform ion implantation to create p-n junctions for the light emitting diode and light detecting diode. By utilizing the SOI wafer's backside, the structure and method increases the number of light emitting diodes and light detecting diodes that can be formed on a SOI wafer, enables an increase in overall device density for an integrated circuit, and reduces attenuation of light signals being emitted and detected by the diodes.

Abstract: A structure and method for fabricating a light emitting diode and a light detecting diode on a silicon-on-insulator (SOI) wafer is provided. Specifically, the structure and method involves forming a light emitting diode and light detecting diode on the SOI wafer's backside and utilizing a deep trench formed in the wafer as an alignment marker. The alignment marker can be detected by x-ray diffraction, reflectivity, or diffraction grating techniques. Moreover, the alignment marker can be utilized to pattern openings and perform ion implantation to create p-n junctions for the light emitting diode and light detecting diode. By utilizing the SOI wafer's backside, the structure and method increases the number of light emitting diodes and light detecting diodes that can be formed on a SOI wafer, enables an increase in overall device density for an integrated circuit, and reduces attenuation of light signals being emitted and detected by the diodes.

Abstract: A method, structure, system of aligning a substrate to a photomask. The method comprising: directing light through a clear region of the photomask in a photolithography tool, through a lens of the tool and onto a set of at least three diffraction minor arrays on the substrate, each diffraction minor array of the set of at least three diffraction minor arrays comprising a single row of minors, all mirrors in any particular diffraction minor array spaced apart a same distance, minors in different diffraction minor arrays spaced apart different distances; measuring an intensity of light diffracted from the set of at least three diffraction mirror arrays onto an array of photo detectors; and adjusting a temperature of the photomask or photomask and lens based on the measured intensity of light.

Abstract: A semiconductor wafer comprises a first chip and a second chip, each chip comprising a core, link layer and physical layer. A kerf area physically connects the two chips on the wafer, and a kerf area interconnect selectively couples the link layers of the two chips while the two physical layers are disabled.

Abstract: A method, structure, system of aligning a substrate to a photomask. The method comprising: directing light through a clear region of the photomask in a photolithography tool, through a lens of the tool and onto a set of at least three diffraction mirror arrays on the substrate, each diffraction mirror array of the set of at least three diffraction minor arrays comprising a single row of mirrors, all mirrors in any particular diffraction mirror array spaced apart a same distance, mirrors in different diffraction mirror arrays spaced apart different distances; measuring an intensity of light diffracted from the set of at least three diffraction mirror arrays onto an array of photo detectors; and adjusting a temperature of the photomask or photomask and lens based on the measured intensity of light.

Abstract: A method, system and computer program product for partitioning the binary image of a software program, and partially removing code bits to create an encrypted software key, to increase software security. The software program's binary image is partitioned along a random segment length or a byte/nibble segment length, and the code bits removed, and stored, along with their positional data in a software key. The software key is encrypted and is separately distributed from the inoperable binary image to the end user. The encrypted key is stored on a secure remote server. When the end user properly authenticates with the developer's remote servers, the encrypted security key is downloaded from the secure remote server and is locally decrypted. The removed code bits are reinserted into the fractioned binary image utilizing the positional location information. The binary image is then operable to complete execution of the software program.

Abstract: A method, structure, system of aligning a substrate to a photomask. The method comprising: directing light through a clear region of the photomask in a photolithography tool, through a lens of the tool and onto a set of at least three diffraction mirror arrays on the substrate, each diffraction mirror array of the set of at least three diffraction mirror arrays comprising a single row of mirrors, all mirrors in any particular diffraction mirror array spaced apart a same distance, mirrors in different diffraction mirror arrays spaced apart different distances; measuring an intensity of light diffracted from the set of at least three diffraction mirror arrays onto an array of photo detectors; and adjusting a temperature of the photomask or photomask and lens based on the measured intensity of light.

Abstract: System and method for designing an electronic package. A placement manager receives a physical design of an electronic package from a packaging design tool. The placement manager receives design constraints regarding the physical design for the electronic package. The placement manager inserts specifications for at least one de-gassing opening in the physical design for the electronic package, wherein the specification for at least one de-gassing opening are created in accordance with said design constraints regarding said physical design of said electronic package. The placement manager outputs an updated physical design of the electronic package.

Abstract: A scalable electronic package assembly for memory devices and other terminated bus structures is disclosed. The scalable electronic package assembly includes a first electronic carrier and a second electronic carrier. The first electronic carrier includes a first set of electronic devices controlled by a controller. The second electronic carrier includes a second set of electronic devices that are also controlled by the controller on the first electronic carrier. The second electronic carrier is electrically connected to the first electronic carrier via multiple solder columns. The second electronic carrier is physically stacked on top of the first electronic carrier via an insulator.

Abstract: A method, system and computer program product for preventing execution of pirated software. A file is loaded on an end user's computer containing a binary image that is generated by removing one or more code bits from an executable code. A request is sent to a remote server to return a software key required for execution of the executable code from the binary image. The software key is downloaded to the end user's computer on which the binary image is loaded. One or more bits from the software key is inserted into the appropriate location of the binary image to regenerate the executable code. The executable code is enabled for execution on the end user's computer only following the embedding of the one or more bits.

Abstract: A method, system and computer program product for partitioning the binary image of a software program, and partially removing code bits to create an encrypted software key, to increase software security. The software program's binary image is partitioned along a random segment length or a byte/nibble segment length, and the code bits removed, and stored, along with their positional data in a software key. The software key is encrypted and is separately distributed from the inoperable binary image to the end user. The encrypted key is stored on a secure remote server. When the end user properly authenticates with the developer's remote servers, the encrypted security key is downloaded from the secure remote server and is locally decrypted. The removed code bits are reinserted into the fractioned binary image utilizing the positional location information. The binary image is then operable to complete execution of the software program.

Abstract: System and method for designing an electronic package. A placement manager receives a physical design of an electronic package from a packaging design tool. The placement manager receives design constraints regarding the physical design for the electronic package. The placement manager inserts specifications for at least one de-gassing opening in the physical design for the electronic package, wherein the specification for at least one de-gassing opening are created in accordance with said design constraints regarding said physical design of said electronic package. The placement manager outputs an updated physical design of the electronic package.