Patents by Inventor Trevor M. Lanting
Trevor M. Lanting has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240086748Abstract: The systems, devices, articles, and methods described herein generally relate to analog computers, for example quantum processors comprising qubits, couplers, and, or cavities. Analog computers, for example quantum processor based computers, are the subject of various sources of error which can hinder operation, potentially reducing computational accuracy and speed. Sources of error can be broadly characterized, for example as i) a background susceptibility do to inherently characteristics of the circuitry design, ii) as an h/J ratio imbalance, iii) bit flip errors, iv) fidelity, and v) Anderson localization, and various combinations of the aforesaid.Type: ApplicationFiled: September 13, 2023Publication date: March 14, 2024Inventors: Paul I. Bunyk, James King, Murray C. Thom, Mohammad H. Amin, Anatoly Smirnov, Sheir Yarkoni, Trevor M. Lanting, Andrew D. King, Kelly T. R. Boothby
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Patent number: 11880741Abstract: Generate an automorphism of the problem graph, determine an embedding of the automorphism to the hardware graph and modify the embedding of the problem graph into the hardware graph to correspond to the embedding of the automorphism to the hardware graph. Determine an upper-bound on the required chain strength. Calibrate and record properties of the component of a quantum processor with a digital processor, query the digital processor for a range of properties. Generate a bit mask and change the sign of the bias of individual qubits according to the bit mask before submitting a problem to a quantum processor, apply the same bit mask to the bit result. Generate a second set of parameters of a quantum processor from a first set of parameters via a genetic algorithm.Type: GrantFiled: August 7, 2020Date of Patent: January 23, 2024Assignee: D-WAVE SYSTEMS INC.Inventors: Robert B. Israel, Trevor M. Lanting, Andrew D. King
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Patent number: 11856871Abstract: Systems and methods for fabricating a superconducting integrated circuit that includes wiring layers comprising low-noise material are described. A superconducting integrated circuit can be implemented in a computing system that includes a quantum processor. Such a superconducting integrated circuit includes a first set of one or more wiring layers that form a noise-susceptible superconducting device that can decrease processor when exposed to noise. The superconducting integrated circuit can further include a second set of one or more wiring layers that form a superconducting device that is less susceptible to noise. Fabricating a superconducting device that contains low-noise material can include depositing and patterning a wiring layer comprising a first material that is superconductive in a respective range of temperatures and depositing and patterning a different wiring layer comprising a second material that is superconductive in a respective range of temperatures.Type: GrantFiled: February 25, 2022Date of Patent: December 26, 2023Assignee: D-WAVE SYSTEMS INC.Inventors: Trevor M. Lanting, Danica W. Marsden, Byong Hyop Oh, Eric G. Ladizinsky, Shuiyuan Huang, J. Jason Yao, Douglas P. Stadtler
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Patent number: 11797874Abstract: The systems, devices, articles, and methods described herein generally relate to analog computers, for example quantum processors comprising qubits, couplers, and, or cavities. Analog computers, for example quantum processor based computers, are the subject of various sources of error which can hinder operation, potentially reducing computational accuracy and speed. Sources of error can be broadly characterized, for example as i) a background susceptibility do to inherently characteristics of the circuitry design, ii) as an h/J ratio imbalance, iii) bit flip errors, iv) fidelity, and v) Anderson localization, and various combinations of the aforesaid.Type: GrantFiled: July 28, 2021Date of Patent: October 24, 2023Assignee: 1372934 B.C. LTD.Inventors: Paul I. Bunyk, James King, Murray C. Thom, Mohammad H. Amin, Anatoly Smirnov, Sheir Yarkoni, Trevor M. Lanting, Andrew D. King, Kelly T. R. Boothby
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Publication number: 20230027682Abstract: An analog computing system having a qubit which is provided with inductors positioned near to the qubit's Josephson junctions and inductors positioned far from the qubit's Josephson junctions. The near inductors exhibit capacitance-reducing behavior and the far inductors exhibit capacitance-increasing behavior as their respective inductances are increased. Near and far inductors can be tuned to homogenize the capacitance of the qubit across a range of programmable states based on predicted and target capacitance for the qubit. The inductors may be tuned to homogenize both capacitance and inductance.Type: ApplicationFiled: December 15, 2020Publication date: January 26, 2023Inventors: Reza Molavi, Mark H. Volkmann, Emile M. Hoskinson, Richard G. Harris, Trevor M. Lanting, Paul I. Bunyk, Andrew J. Berkley
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Patent number: 11494683Abstract: Josephson junctions (JJ) may replace primary inductance of transformers to realize galvanic coupling between qubits, advantageously reducing size. A long-range symmetric coupler may include a compound JJ (CJJ) positioned at least approximately at a half-way point along the coupler to advantageously provide a higher energy of a first excited state than that of an asymmetric long-range coupler. Quantum processors may include qubits and couplers with a non-stoquastic Hamiltonian to enhance multi-qubit tunneling during annealing. Qubits may include additional shunt capacitances, e.g., to increase overall quality of a total capacitance and improve quantum coherence. A sign and/or magnitude of an effective tunneling amplitude ?eff of a qubit characterized by a double-well potential energy may advantageously be tuned. Sign-tunable electrostatic coupling of qubits may be implemented, e.g., via resonators, and LC-circuits. YY couplings may be incorporated into a quantum anneaier (e.g., quantum processor).Type: GrantFiled: December 19, 2018Date of Patent: November 8, 2022Assignee: D-WAVE SYSTEMS INC.Inventors: Mohammad H. Amin, Paul I. Bunyk, Trevor M. Lanting, Chunqing Deng, Anatoly Smirnov, Kelly T. R. Boothby, Emile M. Hoskinson, Christopher B. Rich
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Publication number: 20220263007Abstract: Systems and methods for fabricating a superconducting integrated circuit that includes wiring layers comprising low-noise material are described. A superconducting integrated circuit can be implemented in a computing system that includes a quantum processor. Such a superconducting integrated circuit includes a first set of one or more wiring layers that form a noise-susceptible superconducting device that can decrease processor when exposed to noise. The superconducting integrated circuit can further include a second set of one or more wiring layers that form a superconducting device that is less susceptible to noise. Fabricating a superconducting device that contains low-noise material can include depositing and patterning a wiring layer comprising a first material that is superconductive in a respective range of temperatures and depositing and patterning a different wiring layer comprising a second material that is superconductive in a respective range of temperatures.Type: ApplicationFiled: February 25, 2022Publication date: August 18, 2022Inventors: Trevor M. Lanting, Danica W. Marsden, Byong Hyop Oh, Eric G. Ladizinsky, Shuiyuan Huang, J. Jason Yao, Douglas P. Stadtler
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Patent number: 11288073Abstract: A hybrid processor includes a classical (digital) processor and a quantum processor and implements a calibration procedure to calibrate devices in the quantum processor. Parameter measurements are defined as vertices in a directed acyclic graph. Dependencies between measurements are defined as directed edges between vertices. The calibration procedure orders the vertices, respecting the order of the dependencies while at least attempting to reduce the time needed to perform all the measurements. The calibration procedure provides a level of abstraction to allow non-expert users to use the calibration procedure. Each vertex has a set of attributes defining the status of the measurement, time of the measurement and value of the measurement.Type: GrantFiled: April 21, 2020Date of Patent: March 29, 2022Assignee: D-WAVE SYSTEMS INC.Inventors: Andrew J. Berkley, Ilya V. Perminov, Mark W. Johnson, Christopher B. Rich, Fabio Altomare, Trevor M. Lanting
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Publication number: 20220019929Abstract: The systems, devices, articles, and methods described herein generally relate to analog computers, for example quantum processors comprising qubits, couplers, and, or cavities. Analog computers, for example quantum processor based computers, are the subject of various sources of error which can hinder operation, potentially reducing computational accuracy and speed. Sources of error can be broadly characterized, for example as i) a background susceptibility do to inherently characteristics of the circuitry design, ii) as an h/J ratio imbalance, iii) bit flip errors, iv) fidelity, and v) Anderson localization, and various combinations of the aforesaid.Type: ApplicationFiled: July 28, 2021Publication date: January 20, 2022Inventors: Paul I. Bunyk, James King, Murray C. Thom, Mohammad H. Amin, Anatoly Smirnov, Sheir Yarkoni, Trevor M. Lanting, Andrew D. King, Kelly T. R. Boothby
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Patent number: 11100418Abstract: The systems, devices, articles, and methods described herein generally relate to analog computers, for example quantum processors comprising qubits, couplers, and, or cavities. Analog computers, for example quantum processor based computers, are the subject of various sources of error which can hinder operation, potentially reducing computational accuracy and speed. Sources of error can be broadly characterized, for example as i) a background susceptibility do to inherently characteristics of the circuitry design, ii) as an h/J ratio imbalance, iii) bit flip errors, iv) fidelity, and v) Anderson localization, and various combinations of the aforesaid.Type: GrantFiled: February 14, 2019Date of Patent: August 24, 2021Assignee: D-WAVE SYSTEMS INC.Inventors: Paul I. Bunyk, James King, Murray C. Thom, Mohammad H. Amin, Anatoly Yu Smirnov, Sheir Yarkoni, Trevor M. Lanting, Andrew D. King, Kelly T. R. Boothby
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Publication number: 20200379768Abstract: A hybrid processor includes a classical (digital) processor and a quantum processor and implements a calibration procedure to calibrate devices in the quantum processor. Parameter measurements are defined as vertices in a directed acyclic graph. Dependencies between measurements are defined as directed edges between vertices. The calibration procedure orders the vertices, respecting the order of the dependencies while at least attempting to reduce the time needed to perform all the measurements. The calibration procedure provides a level of abstraction to allow non-expert users to use the calibration procedure. Each vertex has a set of attributes defining the status of the measurement, time of the measurement and value of the measurement.Type: ApplicationFiled: April 21, 2020Publication date: December 3, 2020Inventors: Andrew J. Berkley, Ilya V. Perminov, Mark W. Johnson, Christopher B. Rich, Fabio Altomare, Trevor M. Lanting
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Publication number: 20200372393Abstract: Generate an automorphism of the problem graph, determine an embedding of the automorphism to the hardware graph and modify the embedding of the problem graph into the hardware graph to correspond to the embedding of the automorphism to the hardware graph. Determine an upper-bound on the required chain strength. Calibrate and record properties of the component of a quantum processor with a digital processor, query the digital processor for a range of properties. Generate a bit mask and change the sign of the bias of individual qubits according to the bit mask before submitting a problem to a quantum processor, apply the same bit mask to the bit result. Generate a second set of parameters of a quantum processor from a first set of parameters via a genetic algorithm.Type: ApplicationFiled: August 7, 2020Publication date: November 26, 2020Inventors: Robert B. Israel, Trevor M. Lanting, Andrew D. King
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Publication number: 20200320426Abstract: Josephson junctions (JJ) may replace primary inductance of transformers to realize galvanic coupling between qubits, advantageously reducing size. A long-range symmetric coupler may include a compound JJ (CJJ) positioned at least approximately at a half-way point along the coupler to advantageously provide a higher energy of a first excited state than that of an asymmetric long-range coupler. Quantum processors may include qubits and couplers with a non-stoquastic Hamiltonian to enhance multi-qubit tunneling during annealing. Qubits may include additional shunt capacitances, e.g., to increase overall quality of a total capacitance and improve quantum coherence. A sign and/or magnitude of an effective tunneling amplitude ?eff of a qubit characterized by a double-well potential energy may advantageously be tuned. Sign-tunable electrostatic coupling of qubits may be implemented, e.g., via resonators, and LC-circuits. YY couplings may be incorporated into a quantum anneaier (e.g., quantum processor).Type: ApplicationFiled: December 19, 2018Publication date: October 8, 2020Inventors: Mohammad H. AMIN, Paul I. BUNYK, Trevor M. LANTING, Chunqing DENG, Anatoly SMIRNOV, Kelly T.R. BOOTHBY, Emile M. HOSKINSON, Christopher B. RICH
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Patent number: 10789540Abstract: Generate an automorphism of the problem graph, determine an embedding of the automorphism to the hardware graph and modify the embedding of the problem graph into the hardware graph to correspond to the embedding of the automorphism to the hardware graph. Determine an upper-bound on the required chain strength. Calibrate and record properties of the component of a quantum processor with a digital processor, query the digital processor for a range of properties. Generate a bit mask and change the sign of the bias of individual qubits according to the bit mask before submitting a problem to a quantum processor, apply the same bit mask to the bit result. Generate a second set of parameters of a quantum processor from a first set of parameters via a genetic algorithm.Type: GrantFiled: April 13, 2017Date of Patent: September 29, 2020Assignee: D-WAVE SYSTEMS INC.Inventors: Andrew D. King, Robert B. Israel, Paul I. Bunyk, Kelly T. R. Boothby, Steven P. Reinhardt, Aidan P. Roy, James A. King, Trevor M. Lanting, Abraham J. Evert
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Publication number: 20200152851Abstract: Systems and methods for fabricating a superconducting integrated circuit that includes wiring layers comprising low-noise material are described. A superconducting integrated circuit can be implemented in a computing system that includes a quantum processor. Such a superconducting integrated circuit includes a first set of one or more wiring layers that form a noise-susceptible superconducting device that can decrease processor when exposed to noise. The superconducting integrated circuit can further include a second set of one or more wiring layers that form a superconducting device that is less susceptible to noise. Fabricating a superconducting device that contains low-noise material can include depositing and patterning a wiring layer comprising a first material that is superconductive in a respective range of temperatures and depositing and patterning a different wiring layer comprising a second material that is superconductive in a respective range of temperatures.Type: ApplicationFiled: November 12, 2019Publication date: May 14, 2020Inventors: Trevor M. Lanting, Danica W. Marsden, Byong Hyop Oh, Eric G. Ladizinsky, Shuiyuan Huang, J. Jason Yao, Douglas P. Stadtler
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Publication number: 20190266508Abstract: The systems, devices, articles, and methods described herein generally relate to analog computers, for example quantum processors comprising qubits, couplers, and, or cavities. Analog computers, for example quantum processor based computers, are the subject of various sources of error which can hinder operation, potentially reducing computational accuracy and speed. Sources of error can be broadly characterized, for example as i) a background susceptibility do to inherently characteristics of the circuitry design, ii) as an h/J ratio imbalance, iii) bit flip errors, iv) fidelity, and v) Anderson localization, and various combinations of the aforesaid.Type: ApplicationFiled: February 14, 2019Publication date: August 29, 2019Inventors: Paul I. Bunyk, James King, Murray C. Thom, Mohammad H. Amin, Anatoly Yu Smirnov, Sheir Yarkoni, Trevor M. Lanting, Andrew D. King, Kelly T. R. Boothby
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Publication number: 20170300817Abstract: Generate an automorphism of the problem graph, determine an embedding of the automorphism to the hardware graph and modify the embedding of the problem graph into the hardware graph to correspond to the embedding of the automorphism to the hardware graph. Determine an upper-bound on the required chain strength. Calibrate and record properties of the component of a quantum processor with a digital processor, query the digital processor for a range of properties. Generate a bit mask and change the sign of the bias of individual qubits according to the bit mask before submitting a problem to a quantum processor, apply the same bit mask to the bit result. Generate a second set of parameters of a quantum processor from a first set of parameters via a genetic algorithm.Type: ApplicationFiled: April 13, 2017Publication date: October 19, 2017Inventors: Andrew D. King, Robert B. Israel, Paul I. Bunyk, Tomas J. Boothby, Steven P. Reinhardt, Aidan P. Roy, James A. King, Trevor M. Lanting, Abraham J. Evert