Abstract: A method of manufacturing an integrated circuit (IC), comprising: defining a plurality of continuous active areas; forming conducting lines extending over the active areas; and using the conducting lines as a mask, introducing dopant into the active areas. Connections are provided between doped regions and conducting lines to form first and second circuit portions, at least one active area being continuous between those portions. In that active area, connections are provided between doped regions and conducting lines to form a pair of diode-connected transistors in reverse bias to one another between the first and second circuit portions, connected so as to leave a shared, unconnected doped region between the pair. The present invention also relates to a corresponding IC.

Abstract: A method of manufacturing an integrated circuit (IC), comprising: defining a plurality of continuous active areas; forming conducting lines extending over the active areas; and using the conducting lines as a mask, introducing dopant into the active areas. Connections are provided between doped regions and conducting lines to form first and second circuit portions, at least one active area being continuous between those portions. In that active area, connections are provided between doped regions and conducting lines to form a pair of diode-connected transistors in reverse bias to one another between the first and second circuit portions, connected so as to leave a shared, unconnected doped region between the pair. The present invention also relates to a corresponding IC.

Abstract: A method of charging a battery in a system involving a renewable energy source and operable to supply at least some electrical energy from the renewable energy source to a third party involves causing a charge controller operably connected to the renewable energy source to receive the electrical energy from the renewable energy source and operably connected to the battery, to charge the battery, using only the electrical energy from the renewable energy source, according to a charging sequence. The charging sequence includes at least a bulk charge period wherein the battery is charged at a relatively constant charging current, an absorption period following the bulk charge period wherein the battery is charged in an absorption mode, and a float period following the absorption period wherein the battery is charged in a float charging mode.

Abstract: A method of charging a battery in a system involving a renewable energy source and operable to supply at least some electrical energy from the renewable energy source to a third party involves causing a charge controller operably connected to the renewable energy source to receive the electrical energy from the renewable energy source and operably connected to the battery, to charge the battery, using only the electrical energy from the renewable energy source, according to a charging sequence. The charging sequence includes at least a bulk charge period wherein the battery is charged at a relatively constant charging current, an absorption period following the bulk charge period wherein the battery is charged in an absorption mode, and a float period following the absorption period wherein the battery is charged in a float charging mode.

Abstract: A method (300) for optimising transistor performance in semiconductor integrated circuits built from standard cells (12), or custom transistor level layout, is disclosed. An active area of NMOS diffusion is extended with a joining area (102) between two adjacent cells (112) having the same net on diffusion at the adjacent edges of each cell. The diffusion area is extended to limit the occurrence of active and nonactive interface to minimise lattice strain effects and improve transistor performance.

Abstract: A dividing circuit comprises a plurality (N) of transistor stages connected in a ring. Each stage comprises a first pair of transistors of a first conductivity type connected in series between a first voltage level and an output node, a second pair of transistors of a second conductivity type connected in series between a second voltage level and said output node, wherein control nodes of a first transistor of each said transistor pair are connected together to provide an input node for the stage, and control nodes of a second transistor of each said transistor pair are connected together to provide a clock node for the stage, wherein the input node of each stage is connected to the output node of a preceding stage whereby an output signal is generated at each of said output nodes, each cycle of the output signal representing N cycles of a clock signal applied to said clock nodes of the stages, the output signal having a duty cycle that is closer to 50% than a duty cycle of said clock signal.

Abstract: A method for positioning/routing a clock circuit for an integrated circuit compensates for phase differences by adjusting secondary amplifiers having adjustable input delays. The method includes the steps of positioning first conductive lines parallel to a first direction evenly spaced with respect to the second direction. The first conductive lines are connected to outputs of the first amplifiers. A balanced tree-like structure provides each of the first amplifiers a clock signal coming from a single source. The method further includes the steps of positioning functional blocks for forming the integrated circuit, and the positioning of second lines parallel to the second direction. Each secondary amplifier is routed to the closest second line. An equivalent electrical diagram corresponding to the path taken by the clock signal between the input of the tree-like structure device and the input of each secondary amplifier is determined.

Abstract: A programmable dividing circuit comprises a first plurality N of similar transistor stages connected in a divide-by-N sequence, wherein N is an odd integer, the transistor stages being configured so that when an output of the last stage is supplied to a first stage in the sequence, the dividing circuit operates as a divide-by-N circuit in which an output signal is generated which has one cycle for every N cycles of a clock signal applied to the transistor stages.

Abstract: A dividing circuit comprises, connected in a ring, a plurality M of transistor stages, where M is an even integer. Each transistor stage comprises an input node, a clock node and an output node. A tri-state inverter stage has an input node connected to the output node of a preceding transistor stage in the ring, an enable node connected to the clock nodes of the transistor stages, and an output node connected to the input node of a subsequent transistor stage in the ring.

Abstract: An off-chip driver circuit can operate in an output mode to drive a signal supplied at its input terminals to an output terminal. It can also operate in an input mode in which signals are driven from an external circuit via the output terminal onto the chip. In an output mode, the output terminal is clamped to reduce the effect of overshoot voltages, for example as a result of reflections from the external circuits.

Abstract: An off-chip driver circuit having circuitry for providing protection against high voltages when the off-chip driver circuit is disabled is described. The circuitry for providing protection against high voltages utilizes a minimum number of transistors and therefore minimizes the chip area utilized by the off-chip driver circuit. An off-chip driver circuit has an input terminal and an output terminal. A pull-up transistor has a controllable path connected between a first power supply voltage and the output terminal of the off-chip driver circuit, and a control terminal connected to the input terminal via a pass gate connected to isolate the input terminal from high voltages applied to the output terminal. A control transistor has a controllable path connected between the control terminal of the pull-up transistor and the output terminal, and a control terminal connected to a control potential.