Patents by Inventor Trevor N. Mudge
Trevor N. Mudge has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9880843Abstract: A data processing apparatus and method for accessing operands stored within a set of registers. Instruction decoder circuitry, responsive to program instructions, generates register access control signals identifying for each program instruction which registers in the register set are to be accessed by the processing circuitry when performing the processing operation specified by that program instruction. The set of registers are logically arranged as a plurality of register groups, with each register in the set being a member of more than one register group. Each program instruction includes a register specifier field, and instruction decoder circuitry is responsive to each program instruction to determine a selected register group, and to determine one or more selected members of that selected register group. The instruction decoder circuitry then outputs register access control signals identifying the register corresponding to each selected member of the selected register group.Type: GrantFiled: February 1, 2012Date of Patent: January 30, 2018Assignee: The Regents of the University of MichiganInventors: Joseph M Pusdesris, Trevor N Mudge, Thomas D Manville
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Publication number: 20130198487Abstract: A data processing apparatus and method for accessing operands stored within a set of registers. Instruction decoder circuitry, responsive to program instructions, generates register access control signals identifying for each program instruction which registers in the register set are to be accessed by the processing circuitry when performing the processing operation specified by that program instruction. The set of registers are logically arranged as a plurality of register groups, with each register in the set being a member of more than one register group. Each program instruction includes a register specifier field, and instruction decoder circuitry is responsive to each program instruction to determine a selected register group, and to determine one or more selected members of that selected register group. The instruction decoder circuitry then outputs register access control signals identifying the register corresponding to each selected member of the selected register group.Type: ApplicationFiled: February 1, 2012Publication date: August 1, 2013Applicant: The Regents of the University of MichiganInventors: Joseph M. PUSDESRIS, Trevor N. MUDGE, Thomas D. MANVILLE
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Patent number: 8381155Abstract: A method of generating valid vertical interconnect positions for a multiple layer integrated circuit including multiple layers stacked vertically above one another and having a bonding interface between at least one pair of layers. The interface is formed by the coupling of a pair of conductive bond patterns formed on facing surfaces of the pair of layers. The method includes defining a candidate transformation origin, defining a sub-region which tessellates across the patterns, applying a predetermined transformation to the patterns at the bonding interface, determining the validity of the candidate transformation origin in dependence on coincidence of at least a subset of the patterns with the transformed patterns, selecting a valid transformation origin, and defining a set of valid vertical interconnect positions associated with the valid transformation origin at positions in the bonding interface where the original and transformed patterns coincided with each other.Type: GrantFiled: October 3, 2011Date of Patent: February 19, 2013Assignee: The Regents of the University of MichiganInventors: David A. Fick, Ronald G. Dreslinski, Trevor N. Mudge, David T. Blaauw, Dennis M. Sylvester
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Publication number: 20120254491Abstract: Interconnect circuitry 2 has a plurality of data source circuits 8 connected to respective input paths 4 and a plurality of data destination circuits 10 connected to respective output paths 6. Connection cells 12 provide selective connections between input paths 4 and output paths 6. Arbitration circuitry 26 provides adaptive priority arbitration between overlapping requests received at different input paths. Priority bits 16 within a matrix of priority bit 46 for each output path 10 are used to represent the priority relationships between different input paths which compete for access to that output path 10. Update operations are applied on a per row or per column basis within the matrix to implement update schemes such as least recently granted, most recently granted, round robin, reversal, swap, selective least recently granted, selective most recently granted etc.Type: ApplicationFiled: April 4, 2012Publication date: October 4, 2012Applicant: The Regents of the University of MichiganInventors: Sudhir Kumar SATPATHY, David Theodor Blaauw, Dennis Michael Sylvester, Trevor N. Mudge
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Patent number: 7533226Abstract: A memory circuit for use in a data processing circuit is described, in which memory cells have at least two states, each state being determined by both a first voltage level corresponding to a first supply line and a second voltage level corresponding to a second supply line. The memory circuit comprises a readable state in which information stored in a memory cell is readable and an unreadable state in which information stored in said memory cell is reliably retained but unreadable. Changing the first voltage level but keeping the second voltage level substantially constant effects a transition between the readable state and the unreadable state. In use, the static power consumption of the memory cell in the unreadable state is less than static power consumption of the memory cell in the readable state.Type: GrantFiled: February 14, 2006Date of Patent: May 12, 2009Assignees: ARM Limited, University of MichiganInventors: Krisztian Flautner, David T. Blaauw, Trevor N. Mudge, Nam S. Kim, Steven M. Martin
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Patent number: 7260694Abstract: A memory circuit for use in a data processing circuit is described, in which memory cells have at least two states, each state being determined by both a first voltage level corresponding to a first supply line and a second voltage level corresponding to a second supply line. The memory circuit comprises a readable state in which information stored in a memory cell is readable and an unreadable state in which information stored in said memory cell is reliably retained but unreadable. Changing the first voltage level but keeping the second voltage level substantially constant effects a transition between the readable state and the unreadable state. In use, the static power consumption of the memory cell in the unreadable state is less than static power consumption of the memory cell in the readable state.Type: GrantFiled: September 26, 2006Date of Patent: August 21, 2007Assignees: ARM Limited, University of MichiganInventors: Krisztian Flautner, Trevor N. Mudge
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Patent number: 7055007Abstract: A memory circuit for use in a data processing circuit is described, in which memory cells have at least two states, each state being determined by both a first voltage level corresponding to a first supply line and a second voltage level corresponding to a second supply line. The memory circuit comprises a readable state in which information stored in a memory cell is readable and an unreadable state in which information stored in said memory cell is reliably retained but unreadable. Changing the first voltage level but keeping the second voltage level substantially constant effects a transition between the readable state and the unreadable state. In use, the static power consumption of the memory cell in the unreadable state is less than static power consumption of the memory cell in the readable state.Type: GrantFiled: April 10, 2003Date of Patent: May 30, 2006Assignees: ARM Limited, University of MichiganInventors: Krisztian Flautner, David T. Blaauw, Trevor N. Mudge, Nam S. Kim, Steven M. Martin
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Publication number: 20040210728Abstract: A memory circuit for use in a data processing circuit is described, in which memory cells have at least two states, each state being determined by both a first voltage level corresponding to a first supply line and a second voltage level corresponding to a second supply line. The memory circuit comprises a readable state in which information stored in a memory cell is readable and an unreadable state in which information stored in said memory cell is reliably retained but unreadable. Changing the first voltage level but keeping the second voltage level substantially constant effects a transition between the readable state and the unreadable state. In use, the static power consumption of the memory cell in the unreadable state is less than static power consumption of the memory cell in the readable state.Type: ApplicationFiled: April 10, 2003Publication date: October 21, 2004Inventors: Krisztian Flautner, David T. Blaauw, Trevor N. Mudge, Nam S. Kim, Steven M. Martin
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Patent number: 4510616Abstract: A pipeline of programmable serial neighborhood stages is used to automatically check for adherence to a set of predetermined geometrical constraints or design rules used in the fabrication of electronic components such as integrated circuit devices. In a disclosed embodiment, bit-map representations of several IC masks are superimposed in one composite image matrix for processing in the pipeline. Advantages in processing speed, especially for design rule checking requiring data from more than one mask, are obtained since all necessary data is available to the stages in the pipeline.Type: GrantFiled: February 6, 1984Date of Patent: April 9, 1985Assignee: The Environmental Research Institute of MichiganInventors: Robert M. Lougheed, Trevor N. Mudge
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Patent number: 4441207Abstract: A pipeline of programmable serial neighborhood stages is used to automatically check for adherence to a set of predetermined geometrical constraints or design rules used in the fabrication of electronic components such as integrated circuit devices. In a disclosed embodiment, bit-map representations of several IC masks are superimposed in one composite image matrix for processing in the pipeline. Advantages in processing speed, especially for design rule checking requiring data from more than one mask, are obtained since all necessary data is available to the stages in the pipeline.Type: GrantFiled: January 19, 1982Date of Patent: April 3, 1984Assignees: Environmental Research Institute of Michigan, Regents of the University of MichiganInventors: Robert M. Lougheed, Trevor N. Mudge