Abstract: A sequence identification apparatus comprising a processor, wherein the apparatus is adapted to access a directed acyclic graph data structure of equivalence classes of events in event sequences identified in a plurality of time-ordered events, and wherein the graph is optimized such that initial and final sub-sequences of event sequences having common equivalence classes are combined in the graph, the apparatus comprising: a code generator adapted to generate executable code corresponding to the graph such that the code includes an instruction sequence for each event classification of the graph, the code sequence for an event classification being adapted to evaluate criteria to determine if an event corresponds to the event classification; a virtual machine adapted to execute the generated executable code such that, in use, the executable code filters incoming time-ordered events based on the graph.

Abstract: A system controller (20, 100, 30, 40) comprises a receiver (20) for receiving data about a system (10, 11) to be controlled and for associating the received data with a time factor; a summarizer (100) for updating a set of summary bins, each of which covers a respective period of time, and each of which stores a summary of the received data having, a time factor which falls within the respective period of time covered by the summary bin; a processor (30) for, processing the summary bins, for example in order to categorize an unknown entity (5) (such as a human user) interacting with the system under control (10, 11) (via a user interface (11) forming part of the system under control) such as into an adult interested in football, etc., and a director (40) for issuing control instructions to the system to be controlled based on the results of the processor (30).

Abstract: A sequence identification apparatus comprising a processor, wherein the apparatus is adapted to generate a directed acyclic graph data structure of equivalence classes of events in an event sequence identified in a plurality of time-ordered events, wherein the apparatus is further adapted to add a representation of one or more further event sequences to the graph such that one or more of initial and final sub-sequences of sequences having common equivalence classes are combined in the graph.

Abstract: A sequence identification apparatus comprising a processor, wherein the apparatus is adapted to access a directed acyclic graph data structure of equivalence classes of events in event sequences identified in a plurality of time-ordered events, and wherein the graph is optimized optimised such that initial and final sub-sequences of event sequences having common equivalence classes are combined in the graph, the apparatus comprising: a code generator adapted to generate executable code corresponding to the graph such that the code includes an instruction sequence for each event classification of the graph, the code sequence for an event classification being adapted to evaluate criteria to determine if an event corresponds to the event classification; a virtual machine adapted to execute the generated executable code such that, in use, the executable code filters incoming time-ordered events based on the graph.

Abstract: A system controller (20, 100, 30, 40) comprises a receiver (20) for receiving data about a system (10, 11) to be controlled and for associating the received data with a time factor; a summariser (100) for updating a set of summary bins, each of which covers a respective period of time, and each of which stores a summary of the received data having, a time factor which falls within the respective period of time covered by the summary bin; a processor (30) for, processing the summary bins, for example in order to categorise an unknown entity (5) (such as a human user) interacting with the system under control (10, 11) (via a user interface (11) forming part of the system under control) such as into an adult interested in football, etc., and a director (40) for issuing control instructions to the system to be controlled based on the results of the processor (30).