Abstract: The present invention provides a method and system for bypassing defective sections with a memory array of a computer chip. The circuit in accordance with the present invention includes a register for controlling the effective size of the memory array based upon the detection of at least one defective section in the memory array, and a multiplexer for receiving an index address for the memory array and for the mapping of the index address based upon the register means. The circuit in accordance with the present invention does not use fuses to conduct repairs and thus does not require additional area on the chip for such fuses. As such, it eliminates the complications in the manufacturing process related to fuses and redundant cells. The circuit in accordance with the present invention dynamically manipulates the address of the array to bypass the defective regions of the array.

Abstract: A method and system for manufacturing integrated circuit devices having multiple memory units embedded therein. Initially, a single reusable configurable test circuit is fabricated within an integrated circuit device. A number and type of each memory unit embedded within the integrated circuit device are then identified. Finally, the single reusable configurable test circuit is configured, in response to the identifying of a number and type of each memory unit, such that only one test circuit is required for use with multiple integrated circuit devices having multiple diverse memory units embedded therein. The single reusable configurable test circuit can be placed within or outside a fixed core of the integrated circuit device. In addition, the single reusable configurable test circuit can include array built-in self test (ABIST) controller which includes a hierarchical memory configuration that includes a state machine, address counter, compare register and data pattern generator.