Patents by Inventor Trey A. Roessig
Trey A. Roessig has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11870348Abstract: An integrated circuit device includes: an input stage configured to receive first and a second input signals and generate a first voltage based on the first input signal and generate a second voltage based on the second input signal; an amplification stage configured to generate a first output current based on the first voltage and a second output current based on the second voltage; a bias stage configured to generate a bias voltage for the amplification stage based on the first and second voltages; a load stage configured to output a differential voltage signal proportional to a current through a device for which current is sensed based on a comparison of the first and second output currents; and an output stage configured to output a signal to control a duty cycle of the device for which current is sensed.Type: GrantFiled: August 19, 2021Date of Patent: January 9, 2024Assignee: Empower Semiconductor, Inc.Inventors: Narendra Nath Gaddam, Trey Roessig
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Patent number: 11870343Abstract: A converter circuit. In one aspect, the converter circuit includes an input terminal, a first output terminal and a second output terminal, and first, second, third and fourth capacitors coupled to a plurality of switches, where the plurality of switches are arranged to repetitively cycle the first, second, third and fourth capacitors between a first state and a second state to generate first and a second output voltages, where in the first state, the first and second capacitors are connected in parallel with each other and in series with a third capacitor to apply a first fraction of an input voltage at the first output terminal, and in the second state, the first and second capacitors are connected in series with each other and in parallel with the fourth capacitor to apply a second fraction of the input voltage at the second output terminal.Type: GrantFiled: December 14, 2022Date of Patent: January 9, 2024Assignee: Empower Semiconductor, Inc.Inventor: Trey Roessig
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Patent number: 11848613Abstract: A multiphase switching converter includes: a plurality of phases, an output capacitor, and a control loop. Each phase includes: a current detection device, a pulse width modulator, a set of switching devices, and an inductor. The control loop is configured to generate a first current signal to the current detection device of each phase of the plurality of phases. The first current signal is proportional to an average current generated by the plurality of phases. The current detection device of each phase provides a signal to a corresponding PWM to control a duty cycle of the set of switching devices to equalize the current generated by each phase and maintain a charge balance on the output capacitor.Type: GrantFiled: August 24, 2021Date of Patent: December 19, 2023Assignee: Empower Semiconductor, Inc.Inventors: Narendra Nath Gaddam, Trey Roessig
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Publication number: 20230280811Abstract: An electronic system includes a circuit board including a power plane. An integrated circuit (e.g., processor) is attached to a first side of the circuit board and is arranged to receive power from the power plane. A plurality of DC-to-DC converters are attached to a second side of the circuit board and are arranged to transfer power to the power plane. Each DC-to-DC converter includes a respective voltage sense input that is electrically connected to a separate location on the power plane. A telemetry circuit is coupled to each of the plurality of DC-to-DC converters and is configured to detect a quantity of power transferred to the common power plane from each of the plurality of power conversion devices.Type: ApplicationFiled: March 2, 2023Publication date: September 7, 2023Applicant: Empower Semiconductor, Inc.Inventors: Trey Roessig, Timothy Alan Phillips, David Lidsky, Gerhard Schrom, Yali Xiong, Artin Der Minassians
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Publication number: 20230215821Abstract: A configurable capacitance device includes a semiconductor substrate including a plurality of integrally formed capacitors; and a separate interconnect structure coupled to the semiconductor substrate, wherein the separate interconnect structure is configurable to electrically couple two or more of the plurality of integrally formed capacitors together in a parallel configuration.Type: ApplicationFiled: October 4, 2022Publication date: July 6, 2023Applicant: Empower Semiconductor, Inc.Inventors: Parag Oak, Timothy Alan Phillips, Trey Roessig, Peter Huang
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Publication number: 20230124931Abstract: A capacitance device includes: a semiconductor substrate; a capacitor disposed on the semiconductor substrate and including first and second positive terminals and first and second negative terminals; a passivation layer formed over the capacitor, the first and second positive terminals and the first and second negative terminals, the passivation layer defining first and second openings over the first and second positive terminals, respectively, a third opening over the first negative terminal and a fourth opening over the second negative terminal; a first metallic bump disposed on the passivation layer and including first extending portions that extend through each of the first and second openings, electrically coupling the first and second positive terminals; and a second metallic bump disposed on the passivation layer and including second extending portions that extend through each of the third and fourth openings, electrically coupling the first and second negative terminals.Type: ApplicationFiled: October 20, 2021Publication date: April 20, 2023Applicant: Empower Semiconductor, Inc.Inventors: Parag Oak, Timothy Alan Phillips, Trey Roessig, Peter Huang, Artin Der Minassians
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Patent number: 11552561Abstract: A converter circuit. In one aspect, the converter circuit includes an input terminal, a first output terminal and a second output terminal, and first, second, third and fourth capacitors coupled to a plurality of switches, where the plurality of switches are arranged to repetitively cycle the first, second, third and fourth capacitors between a first state and a second state to generate first and a second output voltages, where in the first state, the first and second capacitors are connected in parallel with each other and in series with a third capacitor to apply a first fraction of an input voltage at the first output terminal, and in the second state, the first and second capacitors are connected in series with each other and in parallel with the fourth capacitor to apply a second fraction of the input voltage at the second output terminal.Type: GrantFiled: June 28, 2022Date of Patent: January 10, 2023Assignee: Empower Semiconductor, Inc.Inventor: Trey Roessig
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Patent number: 11495554Abstract: A configurable capacitance device includes a semiconductor substrate including a plurality of integrally formed capacitors; and a separate interconnect structure coupled to the semiconductor substrate, wherein the separate interconnect structure is configurable to electrically couple two or more of the plurality of integrally formed capacitors together in a parallel configuration.Type: GrantFiled: October 30, 2020Date of Patent: November 8, 2022Assignee: Empower Semiconductor, Inc.Inventors: Parag Oak, Timothy Alan Phillips, Trey Roessig, Peter Huang
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Publication number: 20210257909Abstract: A power conversion device includes: a semiconductor substrate; a plurality of controllers formed on the semiconductor substrate; two or more converter phases formed on the semiconductor substrate; two or more programmable components formed on the semiconductor substrate, each of the programmable components connected to a respective one of the two or more converter phases; and an interconnect circuit formed on the semiconductor substrate. The two or more programmable components are programmable to selectively couple the two or more converter phases to the plurality of controllers via the interconnect circuit.Type: ApplicationFiled: February 12, 2021Publication date: August 19, 2021Applicant: Empower Semiconductor, Inc.Inventors: Trey Roessig, Parag Oak, Shrinivasan Jaganathan, Narendra Gaddam
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Publication number: 20210134740Abstract: A configurable capacitance device includes a semiconductor substrate including a plurality of integrally formed capacitors; and a separate interconnect structure coupled to the semiconductor substrate, wherein the separate interconnect structure is configurable to electrically couple two or more of the plurality of integrally formed capacitors together in a parallel configuration.Type: ApplicationFiled: October 30, 2020Publication date: May 6, 2021Applicant: Empower Semiconductor, Inc.Inventors: Parag Oak, Timothy Alan Phillips, Trey Roessig, Peter Huang
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Patent number: 10559559Abstract: Disclosed are systems, devices, circuits, components, mechanisms, and processes in which a switching mechanism can be coupled between components. The switching mechanism is configured to have an on state or an off state, where the on state allows current to pass along a current path. A monitoring mechanism has one or more sensing inputs coupled to sense an electrical characteristic at the current path. The electrical characteristic can be a current, voltage, and/or power by way of example. The monitoring mechanism is configured to output a reporting signal indicating the sensed electrical characteristic. The monitoring mechanism can be integrated with the switching mechanism on a chip.Type: GrantFiled: May 17, 2017Date of Patent: February 11, 2020Assignee: Volterra Semiconductor CorporationInventors: David Lidsky, Ognjen Djekic, Ion Elinor Opris, Budong You, Anthony J. Stratakos, Alexandr Ikriannikov, Biljana Beronja, Trey Roessig
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Publication number: 20170256532Abstract: Disclosed are systems, devices, circuits, components, mechanisms, and processes in which a switching mechanism can be coupled between components. The switching mechanism is configured to have an on state or an off state, where the on state allows current to pass along a current path. A monitoring mechanism has one or more sensing inputs coupled to sense an electrical characteristic at the current path. The electrical characteristic can be a current, voltage, and/or power by way of example. The monitoring mechanism is configured to output a reporting signal indicating the sensed electrical characteristic. The monitoring mechanism can be integrated with the switching mechanism on a chip.Type: ApplicationFiled: May 17, 2017Publication date: September 7, 2017Inventors: David Lidsky, Ognjen Djekic, Ion Elinor Opris, Budong You, Anthony J. Stratakos, Alexander Ikriannikov, Biljana Beronja, Trey Roessig
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Patent number: 9679885Abstract: Disclosed are systems, devices, circuits, components, mechanisms, and processes in which a switching mechanism can be coupled between components. The switching mechanism is configured to have an on state or an off state, where the on state allows current to pass along a current path. A monitoring mechanism has one or more sensing inputs coupled to sense an electrical characteristic at the current path. The electrical characteristic can be a current, voltage, and/or power by way of example. The monitoring mechanism is configured to output a reporting signal indicating the sensed electrical characteristic. The monitoring mechanism can be integrated with the switching mechanism on a chip.Type: GrantFiled: April 23, 2012Date of Patent: June 13, 2017Assignee: Volterra Semiconductor CorporationInventors: David Lidsky, Ognjen Djekic, Ion Opris, Budong You, Anthony J. Stratakos, Alexander Ikriannikov, Biljana Beronja, Trey Roessig
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Patent number: 9514262Abstract: A programmable analog tile integrated circuit is configured over a standardized bus by communicating tile configuration information from a first integrated circuit tile, through a second integrated circuit tile, to a third integrated circuit tile. Each of the three integrated circuit tiles is part of an integrated circuit. The standardized bus is formed when the tiles are placed adjacent one another. Data bus and control signal conductors of the adjacent tiles line up and interconnect such that each signal conductor is electrically connected to every tile. Tile configuration information may be written to a selected register identified by an address in any selected one of the tiles using the data bus and control lines, regardless of the relative physical locations of the tile sending and the tile receiving the information. Thus, tile configuration information may pass from one tile to another tile, through any number of intermediate tiles.Type: GrantFiled: March 27, 2015Date of Patent: December 6, 2016Assignee: Active-Semi, Inc.Inventors: Steven Huynh, Matthew A. Grant, Gary M. Hurtz, David J. Kunst, Trey A. Roessig
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Patent number: 9407145Abstract: A regulated, power supply system is described using multiphase DC-DC converters with dynamic fast-turnon, slow-turnoff phase shedding, early phase turn-on, and both load-voltage and drive-transistor feedback to pulsewidth modulators to provide fast response to load transients. In an embodiment, a system master can automatically determine whether all, or only some, slave phase units are fully populated. The programmable system includes fault detection with current and voltage sensing, telemetry capability, and automatic shutdown capability. In an embodiment, these are buck-type converters with or without coupled inductors, however some of the embodiments illustrated include boost configurations.Type: GrantFiled: December 8, 2014Date of Patent: August 2, 2016Assignee: Volterra Semiconductor LLCInventors: Andrew Burstein, Sombuddha Chakraborty, Yali Xiong, Michael D. McJimsey, Trey A. Roessig, Luigi Panseri, Paul H. Choi, Theodore V. Burmas, Biljana Beronja, Giovanni Garcea, Ilija Jergovic, Andrea Pizzutelli, Anthony J. Stratakos
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Publication number: 20150205902Abstract: A programmable analog tile integrated circuit is configured over a standardized bus by communicating tile configuration information from a first integrated circuit tile, through a second integrated circuit tile, to a third integrated circuit tile. Each of the three integrated circuit tiles is part of an integrated circuit. The standardized bus is formed when the tiles are placed adjacent one another. Data bus and control signal conductors of the adjacent tiles line up and interconnect such that each signal conductor is electrically connected to every tile. Tile configuration information may be written to a selected register identified by an address in any selected one of the tiles using the data bus and control lines, regardless of the relative physical locations of the tile sending and the tile receiving the information. Thus, tile configuration information may pass from one tile to another tile, through any number of intermediate tiles.Type: ApplicationFiled: March 27, 2015Publication date: July 23, 2015Inventors: Steven Huynh, Matthew A. Grant, Gary M. Hurtz, David J. Kunst, Trey A. Roessig
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Patent number: 9003340Abstract: A programmable analog tile integrated circuit is configured over a standardized bus by communicating tile configuration information from a first integrated circuit tile, through a second integrated circuit tile, to a third integrated circuit tile. Each of the three integrated circuit tiles is part of an integrated circuit. The standardized bus is formed when the tiles are placed adjacent one another. Data bus and control signal conductors of the adjacent tiles line up and interconnect such that each signal conductor is electrically connected to every tile. Tile configuration information may be written to a selected register identified by an address in any selected one of the tiles using the data bus and control lines, regardless of the relative physical locations of the tile sending and the tile receiving the information. Thus, tile configuration information may pass from one tile to another tile, through any number of intermediate tiles.Type: GrantFiled: January 30, 2009Date of Patent: April 7, 2015Assignee: Active-Semi, Inc.Inventors: Steven Huynh, Matthew A. Grant, Gary M. Hurtz, David J. Kunst, Trey A. Roessig
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Patent number: 8907642Abstract: A regulated, power supply system is described using multiphase DC-DC converters with dynamic fast-turnon, slow-turnoff phase shedding, early phase turn-on, and both load-voltage and drive-transistor feedback to pulsewidth modulators to provide fast response to load transients. In an embodiment, a system master can automatically determine whether all, or only some, slave phase units are fully populated. The programmable system includes fault detection with current and voltage sensing, telemetry capability, and automatic shutdown capability. In an embodiment, these are buck-type converters with or without coupled inductors, however some of the embodiments illustrated include boost configurations.Type: GrantFiled: June 23, 2011Date of Patent: December 9, 2014Assignee: Volterra Semiconductor LLCInventors: Andrew Burstein, Sombuddha Chakraborty, Yali Xiong, Michael D. McJimsey, Trey A. Roessig, Luigi Panseri, Paul H. Choi, Theodore V. Burmas, Biljana Beronja, Giovanni Garcea, Ilija Jergovic, Andrea Pizzutelli, Anthony J. Stratakos
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Patent number: 8581440Abstract: An adaptive phase offset controller for use with a switching power converter having first and second channels. The controller includes a discriminator which detects a ‘critical condition’ in which a switching signal for the first channel transitions during a critical time interval so as to give rise to crosstalk that can corrupt the operation of the second channel's control circuit. When the discriminator detects a critical condition, a phase offset circuit offsets the phase of the first channel's switching signals, such that subsequent transitions occur outside of the critical time interval. A second discriminator and phase offset circuit are preferably employed to detect critical conditions which can give rise to crosstalk that can corrupt the operation of the first channel's control circuit.Type: GrantFiled: August 25, 2010Date of Patent: November 12, 2013Assignee: Analog Devices, Inc.Inventors: Lawrence H. Edelson, Michael P. Daly, Trey Roessig
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Patent number: 8341582Abstract: A programmable analog tile integrated circuit configuration tool communicates a power management control characteristic query soliciting control requirement information for a novel Power Management Integrated Circuit (PMIC) tile in a Multi-Tile Power Management Integrated Circuit (MTPMIC). The configuration tool receives a user response to the query indicating control requirements across a network. The PMIC tile includes configuration registers. Configuration information bit values stored in the configuration registers control the operational characteristics of the functional circuitry of the tile. The configuration registers of each novel PMIC tile are accessible at pre-defined addresses on a standardized bus of the MTPMIC. In response to the user response, the configuration tool generates appropriate tile configuration information for loading the configuration registers such that the PMIC tile within the MTPMIC is programmed to satisfy the user's control requirements.Type: GrantFiled: January 30, 2009Date of Patent: December 25, 2012Assignee: Active-Semi, Inc.Inventors: Steven Huynh, Matthew A. Grant, Gary M. Hurtz, David J. Kunst, Trey A. Roessig