Patents by Inventor Trey Roessig

Trey Roessig has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170256532
    Abstract: Disclosed are systems, devices, circuits, components, mechanisms, and processes in which a switching mechanism can be coupled between components. The switching mechanism is configured to have an on state or an off state, where the on state allows current to pass along a current path. A monitoring mechanism has one or more sensing inputs coupled to sense an electrical characteristic at the current path. The electrical characteristic can be a current, voltage, and/or power by way of example. The monitoring mechanism is configured to output a reporting signal indicating the sensed electrical characteristic. The monitoring mechanism can be integrated with the switching mechanism on a chip.
    Type: Application
    Filed: May 17, 2017
    Publication date: September 7, 2017
    Inventors: David Lidsky, Ognjen Djekic, Ion Elinor Opris, Budong You, Anthony J. Stratakos, Alexander Ikriannikov, Biljana Beronja, Trey Roessig
  • Patent number: 9679885
    Abstract: Disclosed are systems, devices, circuits, components, mechanisms, and processes in which a switching mechanism can be coupled between components. The switching mechanism is configured to have an on state or an off state, where the on state allows current to pass along a current path. A monitoring mechanism has one or more sensing inputs coupled to sense an electrical characteristic at the current path. The electrical characteristic can be a current, voltage, and/or power by way of example. The monitoring mechanism is configured to output a reporting signal indicating the sensed electrical characteristic. The monitoring mechanism can be integrated with the switching mechanism on a chip.
    Type: Grant
    Filed: April 23, 2012
    Date of Patent: June 13, 2017
    Assignee: Volterra Semiconductor Corporation
    Inventors: David Lidsky, Ognjen Djekic, Ion Opris, Budong You, Anthony J. Stratakos, Alexander Ikriannikov, Biljana Beronja, Trey Roessig
  • Patent number: 9514262
    Abstract: A programmable analog tile integrated circuit is configured over a standardized bus by communicating tile configuration information from a first integrated circuit tile, through a second integrated circuit tile, to a third integrated circuit tile. Each of the three integrated circuit tiles is part of an integrated circuit. The standardized bus is formed when the tiles are placed adjacent one another. Data bus and control signal conductors of the adjacent tiles line up and interconnect such that each signal conductor is electrically connected to every tile. Tile configuration information may be written to a selected register identified by an address in any selected one of the tiles using the data bus and control lines, regardless of the relative physical locations of the tile sending and the tile receiving the information. Thus, tile configuration information may pass from one tile to another tile, through any number of intermediate tiles.
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: December 6, 2016
    Assignee: Active-Semi, Inc.
    Inventors: Steven Huynh, Matthew A. Grant, Gary M. Hurtz, David J. Kunst, Trey A. Roessig
  • Patent number: 9407145
    Abstract: A regulated, power supply system is described using multiphase DC-DC converters with dynamic fast-turnon, slow-turnoff phase shedding, early phase turn-on, and both load-voltage and drive-transistor feedback to pulsewidth modulators to provide fast response to load transients. In an embodiment, a system master can automatically determine whether all, or only some, slave phase units are fully populated. The programmable system includes fault detection with current and voltage sensing, telemetry capability, and automatic shutdown capability. In an embodiment, these are buck-type converters with or without coupled inductors, however some of the embodiments illustrated include boost configurations.
    Type: Grant
    Filed: December 8, 2014
    Date of Patent: August 2, 2016
    Assignee: Volterra Semiconductor LLC
    Inventors: Andrew Burstein, Sombuddha Chakraborty, Yali Xiong, Michael D. McJimsey, Trey A. Roessig, Luigi Panseri, Paul H. Choi, Theodore V. Burmas, Biljana Beronja, Giovanni Garcea, Ilija Jergovic, Andrea Pizzutelli, Anthony J. Stratakos
  • Publication number: 20150205902
    Abstract: A programmable analog tile integrated circuit is configured over a standardized bus by communicating tile configuration information from a first integrated circuit tile, through a second integrated circuit tile, to a third integrated circuit tile. Each of the three integrated circuit tiles is part of an integrated circuit. The standardized bus is formed when the tiles are placed adjacent one another. Data bus and control signal conductors of the adjacent tiles line up and interconnect such that each signal conductor is electrically connected to every tile. Tile configuration information may be written to a selected register identified by an address in any selected one of the tiles using the data bus and control lines, regardless of the relative physical locations of the tile sending and the tile receiving the information. Thus, tile configuration information may pass from one tile to another tile, through any number of intermediate tiles.
    Type: Application
    Filed: March 27, 2015
    Publication date: July 23, 2015
    Inventors: Steven Huynh, Matthew A. Grant, Gary M. Hurtz, David J. Kunst, Trey A. Roessig
  • Patent number: 9003340
    Abstract: A programmable analog tile integrated circuit is configured over a standardized bus by communicating tile configuration information from a first integrated circuit tile, through a second integrated circuit tile, to a third integrated circuit tile. Each of the three integrated circuit tiles is part of an integrated circuit. The standardized bus is formed when the tiles are placed adjacent one another. Data bus and control signal conductors of the adjacent tiles line up and interconnect such that each signal conductor is electrically connected to every tile. Tile configuration information may be written to a selected register identified by an address in any selected one of the tiles using the data bus and control lines, regardless of the relative physical locations of the tile sending and the tile receiving the information. Thus, tile configuration information may pass from one tile to another tile, through any number of intermediate tiles.
    Type: Grant
    Filed: January 30, 2009
    Date of Patent: April 7, 2015
    Assignee: Active-Semi, Inc.
    Inventors: Steven Huynh, Matthew A. Grant, Gary M. Hurtz, David J. Kunst, Trey A. Roessig
  • Patent number: 8907642
    Abstract: A regulated, power supply system is described using multiphase DC-DC converters with dynamic fast-turnon, slow-turnoff phase shedding, early phase turn-on, and both load-voltage and drive-transistor feedback to pulsewidth modulators to provide fast response to load transients. In an embodiment, a system master can automatically determine whether all, or only some, slave phase units are fully populated. The programmable system includes fault detection with current and voltage sensing, telemetry capability, and automatic shutdown capability. In an embodiment, these are buck-type converters with or without coupled inductors, however some of the embodiments illustrated include boost configurations.
    Type: Grant
    Filed: June 23, 2011
    Date of Patent: December 9, 2014
    Assignee: Volterra Semiconductor LLC
    Inventors: Andrew Burstein, Sombuddha Chakraborty, Yali Xiong, Michael D. McJimsey, Trey A. Roessig, Luigi Panseri, Paul H. Choi, Theodore V. Burmas, Biljana Beronja, Giovanni Garcea, Ilija Jergovic, Andrea Pizzutelli, Anthony J. Stratakos
  • Patent number: 8581440
    Abstract: An adaptive phase offset controller for use with a switching power converter having first and second channels. The controller includes a discriminator which detects a ‘critical condition’ in which a switching signal for the first channel transitions during a critical time interval so as to give rise to crosstalk that can corrupt the operation of the second channel's control circuit. When the discriminator detects a critical condition, a phase offset circuit offsets the phase of the first channel's switching signals, such that subsequent transitions occur outside of the critical time interval. A second discriminator and phase offset circuit are preferably employed to detect critical conditions which can give rise to crosstalk that can corrupt the operation of the first channel's control circuit.
    Type: Grant
    Filed: August 25, 2010
    Date of Patent: November 12, 2013
    Assignee: Analog Devices, Inc.
    Inventors: Lawrence H. Edelson, Michael P. Daly, Trey Roessig
  • Patent number: 8341582
    Abstract: A programmable analog tile integrated circuit configuration tool communicates a power management control characteristic query soliciting control requirement information for a novel Power Management Integrated Circuit (PMIC) tile in a Multi-Tile Power Management Integrated Circuit (MTPMIC). The configuration tool receives a user response to the query indicating control requirements across a network. The PMIC tile includes configuration registers. Configuration information bit values stored in the configuration registers control the operational characteristics of the functional circuitry of the tile. The configuration registers of each novel PMIC tile are accessible at pre-defined addresses on a standardized bus of the MTPMIC. In response to the user response, the configuration tool generates appropriate tile configuration information for loading the configuration registers such that the PMIC tile within the MTPMIC is programmed to satisfy the user's control requirements.
    Type: Grant
    Filed: January 30, 2009
    Date of Patent: December 25, 2012
    Assignee: Active-Semi, Inc.
    Inventors: Steven Huynh, Matthew A. Grant, Gary M. Hurtz, David J. Kunst, Trey A. Roessig
  • Publication number: 20120293017
    Abstract: Disclosed are systems, devices, circuits, components, mechanisms, and processes in which a switching mechanism can be coupled between components. The switching mechanism is configured to have an on state or an off state, where the on state allows current to pass along a current path. A monitoring mechanism has one or more sensing inputs coupled to sense an electrical characteristic at the current path. The electrical characteristic can be a current, voltage, and/or power by way of example. The monitoring mechanism is configured to output a reporting signal indicating the sensed electrical characteristic. The monitoring mechanism can be integrated with the switching mechanism on a chip.
    Type: Application
    Filed: April 23, 2012
    Publication date: November 22, 2012
    Applicant: VOLTERRA SEMICONDUCTOR CORPORATION
    Inventors: David Lidsky, Ognjen Djekic, Ion Opris, Budong You, Anthony J. Stratakos, Alexander Ikriannikov, Biljana Beronja, Trey Roessig
  • Patent number: 8225260
    Abstract: A programmable analog tile integrated circuit placement tool allows a user to manipulate a graphical representation of a first power management integrated circuit (PMIC) tile with respect to a graphical representation of a second PMIC tile in a proposed Multi-Tile Power Management Integrated Circuit (MTPMIC). The novel PMIC tiles have pre-defined physical structures including a bus portion and a memory structure for storing configuration information for configuring the tile. When appropriately placed in a MTPMIC, the bus portions of the selected tiles automatically form a standardized bus that accommodates all signal communication required for a functioning MTPMIC. A remote user with minimal training in analog circuit design may command the placement of individual tiles in a proposed MTPMIC layout. Upon receiving a user response indicating satisfaction with the placement of PMIC tiles, the tool quickly and automatically generates physical layout data suitable for fabrication of the MTPMIC.
    Type: Grant
    Filed: January 30, 2009
    Date of Patent: July 17, 2012
    Assignee: Active-Semi, Inc.
    Inventors: Steven Huynh, Matthew A. Grant, Gary M. Hurtz, David J. Kunst, Trey A. Roessig
  • Patent number: 8219956
    Abstract: An Analog Tile Selection, Placement, Configuration and Programming (ATSPCP) tool communicates a power management characteristic query over a network. The query is displayed to a user on a webpage. The query is a solicitation for desired characteristics of a Power Management Integrated Circuit (PMIC). After receiving user requirements in a response to the query, the tool selects a number of power management integrated circuit tiles having pre-defined physical structures. The pre-defined structure of each tile includes a bus portion and a memory structure for storing configuring information for the tile. When combined in a Multi-Tile Power Management Integrated Circuit (MTPMIC), the bus portions of the selected tiles automatically form a standardized bus that accommodates all signal communication required for a functioning MTPMIC that meets the user requirements. The ATSPCP tool combines the physical layout data of each selected PMIC tile to form composite physical layout data for the overall MTPMIC.
    Type: Grant
    Filed: January 30, 2009
    Date of Patent: July 10, 2012
    Assignee: Active-Semi, Inc.
    Inventors: Steven Huynh, Matthew A. Grant, Gary M. Hurtz, David J. Kunst, Trey A. Roessig
  • Patent number: 8079007
    Abstract: A programmable analog tile integrated circuit programming tool communicates a power management control characteristic query soliciting control requirement information for a novel power management integrated circuit (PMIC) tile in a multi-tile power management integrated circuit (MTPMIC). The programming tool receives a user response to the query indicating control requirements across a network. The novel PMIC tiles have a pre-defined physical structure including all memory structures required for configuration of each tile and a bus portion. When combined in a multi-tile power management integrated circuit (MTPMIC), the bus portions of the selected tiles automatically form a standardized bus that accommodates all signal communication required for a functioning MTPMIC. The memory structure of each tile is individually addressable via the standardized bus. Thus, in response to control requirements, the programming tool programs a PMIC tile that is part of a MTPMIC to meet the control requirements.
    Type: Grant
    Filed: January 30, 2009
    Date of Patent: December 13, 2011
    Assignee: Active-Semi, Inc.
    Inventors: Steven Huynh, Matthew A. Grant, Gary M. Hurtz, David J. Kunst, Trey A. Roessig
  • Patent number: 8035538
    Abstract: A sigma-delta converter suitable for measuring a photocurrent comprises an input node adapted to receive a current to be measured (Imeas), a capacitor connected to the input node, a clocked comparator coupled to the input node and to a reference voltage Vref at respective inputs, and a switchable current source connected to the input node which conducts a reference current Iref when switched on. The converter is arranged in a sigma-delta configuration, with the current source switched on to pull down the voltage (VCMP) at the input node when the comparator output toggles due to VCMP increasing above Vref, and to be switched off when the comparator output toggles due to VCMP falling below Vref, such that the comparator output comprises a digital bitstream which varies with Imeas.
    Type: Grant
    Filed: December 16, 2009
    Date of Patent: October 11, 2011
    Assignee: Analog Devices, Inc.
    Inventors: Lawrence H. Edelson, Michael P. Daly, Trey A. Roessig
  • Publication number: 20110049986
    Abstract: An adaptive phase offset controller for use with a switching power converter having first and second channels. The controller includes a discriminator which detects a ‘critical condition’ in which a switching signal for the first channel transitions during a critical time interval so as to give rise to crosstalk that can corrupt the operation of the second channel's control circuit. When the discriminator detects a critical condition, a phase offset circuit offsets the phase of the first channel's switching signals, such that subsequent transitions occur outside of the critical time interval. A second discriminator and phase offset circuit are preferably employed to detect critical conditions which can give rise to crosstalk that can corrupt the operation of the first channel's control circuit.
    Type: Application
    Filed: August 25, 2010
    Publication date: March 3, 2011
    Inventors: Lawrence H. EDELSON, Michael P. Daly, Trey Roessig
  • Publication number: 20100199254
    Abstract: A programmable analog tile integrated circuit programming tool communicates a power management control characteristic query soliciting control requirement information for a novel power management integrated circuit (PMIC) tile in a multi-tile power management integrated circuit (MTPMIC). The programming tool receives a user response to the query indicating control requirements across a network. The novel PMIC tiles have a pre-defined physical structure including all memory structures required for configuration of each tile and a bus portion. When combined in a multi-tile power management integrated circuit (MTPMIC), the bus portions of the selected tiles automatically form a standardized bus that accommodates all signal communication required for a functioning MTPMIC. The memory structure of each tile is individually addressable via the standardized bus. Thus, in response to control requirements, the programming tool programs a PMIC tile that is part of a MTPMIC to meet the control requirements.
    Type: Application
    Filed: January 30, 2009
    Publication date: August 5, 2010
    Inventors: Steven Huynh, Matthew A. Grant, Gary M. Hurtz, David J. Kunst, Trey A. Roessig
  • Publication number: 20100199246
    Abstract: A programmable analog tile integrated circuit configuration tool communicates a power management control characteristic query soliciting control requirement information for a novel Power Management Integrated Circuit (PMIC) tile in a Multi-Tile Power Management Integrated Circuit (MTPMIC). The configuration tool receives a user response to the query indicating control requirements across a network. The PMIC tile includes configuration registers. Configuration information bit values stored in the configuration registers control the operational characteristics of the functional circuitry of the tile. The configuration registers of each novel PMIC tile are accessible at pre-defined addresses on a standardized bus of the MTPMIC. In response to the user response, the configuration tool generates appropriate tile configuration information for loading the configuration registers such that the PMIC tile within the MTPMIC is programmed to satisfy the user's control requirements.
    Type: Application
    Filed: January 30, 2009
    Publication date: August 5, 2010
    Inventors: Steven Huynh, Matthew A. Grant, Gary M. Hurtz, David J. Kunst, Trey A. Roessig
  • Publication number: 20100199247
    Abstract: A programmable analog tile integrated circuit is configured over a standardized bus by communicating tile configuration information from a first integrated circuit tile, through a second integrated circuit tile, to a third integrated circuit tile. Each of the three integrated circuit tiles is part of an integrated circuit. The standardized bus is formed when the tiles are placed adjacent one another. Data bus and control signal conductors of the adjacent tiles line up and interconnect such that each signal conductor is electrically connected to every tile. Tile configuration information may be written to a selected register identified by an address in any selected one of the tiles using the data bus and control lines, regardless of the relative physical locations of the tile sending and the tile receiving the information. Thus, tile configuration information may pass from one tile to another tile, through any number of intermediate tiles.
    Type: Application
    Filed: January 30, 2009
    Publication date: August 5, 2010
    Inventors: Steven Huynh, Matthew A. Grant, Gary M. Hurtz, David J. Kunst, Trey A. Roessig
  • Publication number: 20100199250
    Abstract: An Analog Tile Selection, Placement, Configuration and Programming (ATSPCP) tool communicates a power management characteristic query over a network. The query is displayed to a user on a webpage. The query is a solicitation for desired characteristics of a Power Management Integrated Circuit (PMIC). After receiving user requirements in a response to the query, the tool selects a number of power management integrated circuit tiles having pre-defined physical structures. The pre-defined structure of each tile includes a bus portion and a memory structure for storing configuring information for the tile. When combined in a Multi-Tile Power Management Integrated Circuit (MTPMIC), the bus portions of the selected tiles automatically form a standardized bus that accommodates all signal communication required for a functioning MTPMIC that meets the user requirements. The ATSPCP tool combines the physical layout data of each selected PMIC tile to form composite physical layout data for the overall MTPMIC.
    Type: Application
    Filed: January 30, 2009
    Publication date: August 5, 2010
    Inventors: Steven Huynh, Matthew A. Grant, Gary M. Hurtz, David J. Kunst, Trey A. Roessig
  • Publication number: 20100199249
    Abstract: A programmable analog tile integrated circuit placement tool allows a user to manipulate a graphical representation of a first power management integrated circuit (PMIC) tile with respect to a graphical representation of a second PMIC tile in a proposed Multi-Tile Power Management Integrated Circuit (MTPMIC). The novel PMIC tiles have pre-defined physical structures including a bus portion and a memory structure for storing configuration information for configuring the tile. When appropriately placed in a MTPMIC, the bus portions of the selected tiles automatically form a standardized bus that accommodates all signal communication required for a functioning MTPMIC. A remote user with minimal training in analog circuit design may command the placement of individual tiles in a proposed MTPMIC layout. Upon receiving a user response indicating satisfaction with the placement of PMIC tiles, the tool quickly and automatically generates physical layout data suitable for fabrication of the MTPMIC.
    Type: Application
    Filed: January 30, 2009
    Publication date: August 5, 2010
    Inventors: Steven Huynh, Matthew A. Grant, Gary M. Hurtz, David J. Kunst, Trey A. Roessig