Abstract: Apparatus for correcting the byte alignment of multiple-byte data words during DMA word transfers. The apparatus includes a four-byte input word bus and a four-byte output word bus. A carrier register stores the second, third and fourth bytes of a first four-byte data word received on the input bus. A data selector including four 4:1 multiplexers determines which of the three stored word bytes and which of four bytes corresponding to a second data word received on the input bus should be placed on the four-byte output word bus and the sequential order of the bytes on the bus.

Abstract: A circuit for the stable synchronization of an asynchronous data signal. The circuit comprises a first latch for receiving a first asynchronous data signal, a first delayed system clock signal, and a synchronized reset signal and for providing a system clock synchronized version of the first asynchronous data signal. A first delaying circuit receives a system clock signal and the first asynchronous data signal and provides the first delayed system clock signal. The circuit also includes a second latch for receiving a second asynchronous data signal which is a function of the inverse of the first asynchronous data signal and a second delayed system clock signal, and for providing the synchronized reset signal. A second delaying circuit receives the system clock signal and the first asynchronous data signal and provide the second delayed system clock signal.

Abstract: A system is disclosed which reduces the cycle time required for performing virtual look-ahead memory operations in computer systems employing random access memory and paging. In a preferred embodiment of the invention, a processor (CPU) outputs a desired virtual address to an address translation unit (ATU) and to a memory output control unit (MOC) and also outputs processor signals to the ATU and to a memory state generator (MSG). The virtual address is comprised of a first real address and a second virtual address. During a first cycle this first real address is gated through a memory output control unit (MOC) to cause an addressable memory, which is arranged to store data in a page format, to commence memory addressing prior to the completion of translation by the ATU. During the first cycle the ATU translates the second virtual address into second and third real address portions.