Abstract: Methods and devices for blocking orifices and occluding cavities within a patient are provided. The device in one variation comprises first and second tubular members attached to a collapsible sealing element. The device can be placed through an orifice and the collapsible sealing element can be collapsed to seal the orifice. An embolic may be introduced distal to the sealing element to occlude a cavity. The device may incorporate a locking mechanism which can be engaged to lock the sealing element into the collapsed position. The device may incorporate a valve to prevent flow through the tubular members, for example to prevent egress of the embolic from a cavity. The device can be detached to provide a permanent seal of the orifice, and can retain the embolic within the cavity. The device may be used in conjunction with a stent or other retention device to assist the sealing element in maintaining the seal.

Abstract: A SSTL memory interface pre-driver stage that uses a voltage regulator to generate a ‘virtual’ supply is provided. The ‘virtual’ supply, being lower than a power supply voltage of the pre-driver stage, allows low voltage transistors to be used, thereby improving interface performance and decreasing system power consumption. The pre-driver stage uses a biasing circuit to bias the voltage regulator, formed by a transistor arranged in a source follower configuration, to generate the ‘virtual’ supply off which a voltage translator stage of the pre-driver stage operates to generate an output of the pre-driver stage.

Abstract: A SSTL memory interface pre-driver stage that uses a voltage regulator to generate a ‘virtual’ ground reference voltage is provided. The ‘virtual’ ground voltage reference, being greater than a zero volt ground voltage, allows low voltage transistors to be used, thereby improving interface performance and decreasing system power consumption. The pre-driver stage uses a biasing circuit to bias the voltage regulator, formed by a transistor arranged in a source follower configuration, to generate the ‘virtual’ ground reference voltage off which a voltage translator stage of the pre-driver stage operates to generate an output of the pre-driver stage.

Abstract: A SSTL memory interface pre-driver stage that uses a voltage regulator to generate a ‘virtual’ supply is provided. The ‘virtual’ supply, being lower than a power supply voltage of the pre-driver stage, allows low voltage transistors to be used, thereby improving interface performance and decreasing system power consumption. The pre-driver stage uses a biasing circuit to bias the voltage regulator, formed by a transistor arranged in a source follower configuration, to generate the ‘virtual’ supply off which a voltage translator stage of the pre-driver stage operates to generate an output of the pre-driver stage.

Abstract: A SSTL interface voltage translator that uses dynamic biasing to translate an input signal to an output signal is provided. The voltage translator uses a first device that, dependent on a first bias signal, causes the output signal to be pulled down, where the first bias signal is dependent on the input signal. The voltage translator also uses a second device that, dependent on a second bias signal, causes the output signal to be pulled up, where the second bias signal is dependent on the input signal.

Abstract: In one embodiment, a neck bridge for bridging the neck of an aneurysm includes a junction region, a number of radially extending array elements attached to the junction region, and a cover attached to one or both of the junction region and an array element. The array elements are configured to be positioned within the aneurysm after the neck bridge is deployed from a delivery device. In a second embodiment, the neck bridge includes a junction region and a braided or mesh-like structure secured to the junction region. The braided or mesh-like structure is made from an elastic material.

Abstract: A solid state radiation detector for medical imaging incorporates an array of transistors and a continuous radiation detecting layer positioned over the transistors and electrically coupled to the transistors. The transistors may reside on a plurality of tiles, with the continuous radiation detecting layer being disposed over the tiles.

Abstract: A solid state radiation detector provides a plurality of modules disposed adjacent one another in a two-dimensional array. Each of the modules includes an array of thin film transistors. A continuous radiation detecting layer, such as a photoconductor layer, is disposed over the modules. The radiation detecting layer generates electrical charge representative of a pattern of radiation. The thin film transistors are used to sense the electrical charge on a pixel-by-pixel basis to form a representation of an image. A continuous insulating layer can be disposed between the radiation detecting layer and a continuous conducting layer.

Abstract: A solid state radiation detector and fabrication method therefor provide a plurality of modules disposed adjacent one another in a two-dimensional array. Each of the modules includes an array of thin film transistors. A continuous radiation detecting layer, such as a photoconductor layer is disposed over the modules. The radiation detecting layer generates electrical charge representative of a pattern of radiation. The thin film transistors are used to sense the electrical charge on a pixel-by-pixel basis to form a representation of an image. A continuous insulating layer can be disposed between the radiation detecting layer and a continuous conducting layer.