Abstract: An erase-on-demand memory cell 10(1) includes a memory layer 110 and a heating layer 130 that can heat memory layer 110 to at least an erase-effective temperature, to erase its data contents. Memory chips 270(1) and electronic systems 200 include cells 10(1). Electronic systems 200(1) include logic circuitry 210 to issue a signal to initiate heating. Electronic systems 200(2) include memory chips 270(2) with one or more erase-on-demand memory cells 10(2) that include a memory layer 110. One or more reservoirs 262 store chemicals. One or more valves 252 retain the chemicals, and respond to a signal to open, reacting the chemicals and/or exposing memory layers 110 to the chemicals. A method of erasing data contents of memory cells includes determining existence of an erase demand scenario, generating a signal in response to the erase demand scenario, and actuating erasure of the memory cells upon issue of the signal.