Patents by Inventor Trinanjan Chatterjee

Trinanjan Chatterjee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11636244
    Abstract: Some aspects of this disclosure are directed automated performance tuning of a hardware description language (HDL) simulation system. For example, some aspects of this disclosure relate to a method, including generating, by a first subsystem optimizer, a plurality of recommendations corresponding to a first subsystem of a hardware description language (HDL) simulation system. The plurality of recommendations are generated by the first subsystem optimizer using one or more optimization applications. The method further includes generating, by the first subsystem optimizer, a first aggregate recommendation by combining the plurality of recommendations corresponding to the first subsystem of the HDL simulation system. The method further includes updating a configuration of the first subsystem of the HDL simulation system based on the first aggregate recommendation, wherein the HDL simulation system is configured to simulate a circuit design using the updated configuration during execution of the first subsystem.
    Type: Grant
    Filed: September 30, 2021
    Date of Patent: April 25, 2023
    Assignee: SYNOPSYS, INC.
    Inventors: Badri Prasad Gopalan, Melvin Cardozo, Deepesh Puthiya-Purayil, Vamsi Krishna Doppalapudi, Trinanjan Chatterjee, Yichun Wang
  • Patent number: 6132109
    Abstract: This invention provides a method for displaying circuit analysis results corresponding to parts of the circuit near the portion of the hardware description language (HDL) specification that generated that part of the circuit. The invention also includes a method for using probe statements in the HDL specification to mark additional points in the initial circuit that should not be eliminated during optimization. This improves the ability to display circuit analysis results near the appropriate part of the HDL specification.
    Type: Grant
    Filed: June 3, 1994
    Date of Patent: October 17, 2000
    Assignee: Synopsys, Inc.
    Inventors: Brent Gregory, Trinanjan Chatterjee, Jing C. Lin, Srinivas Raghvendra, Emil Girczyc, Paul Estrada, Andrew Seawright
  • Patent number: 5937190
    Abstract: A digital circuit is synthesized from a text description of a digital system. During synthesis, a parse tree with parse nodes is constructed and retained. The relationship between the parse nodes and the circuit elements synthesized from those parse nodes is retained. Using that relationship, analysis results associated with circuit elements can be related to the text that generated those circuit elements. In particular, the analysis results can be used to set the display characteristics, such as font or size, of the text associated with those results.
    Type: Grant
    Filed: April 3, 1995
    Date of Patent: August 10, 1999
    Assignee: Synopsys, Inc.
    Inventors: Brent Gregory, Trinanjan Chatterjee, Jing C. Lin, Srinivas Raghvendra, Emil Girczyc, Paul Estrada, Andrew Seawright