Patents by Inventor Trinh Hai Dang
Trinh Hai Dang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11637239Abstract: The present disclosure, in some embodiments, relates to a resistive random access memory (RRAM) cell. The RRAM cell has a bottom electrode over a substrate. A data storage layer is over the bottom electrode and has a first thickness. A capping layer is over the data storage layer. The capping layer has a second thickness that is in a range of between approximately 1.9 and approximately 3 times thicker than the first thickness. A top electrode is over the capping layer.Type: GrantFiled: August 14, 2019Date of Patent: April 25, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Trinh Hai Dang, Hsing-Lien Lin, Cheng-Yuan Tsai, Chin-Chieh Yang, Yu-Wen Liao, Wen-Ting Chu, Chia-Shiung Tsai
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Publication number: 20190371999Abstract: The present disclosure, in some embodiments, relates to a resistive random access memory (RRAM) cell. The RRAM cell has a bottom electrode over a substrate. A data storage layer is over the bottom electrode and has a first thickness. A capping layer is over the data storage layer. The capping layer has a second thickness that is in a range of between approximately 1.9 and approximately 3 times thicker than the first thickness. A top electrode is over the capping layer.Type: ApplicationFiled: August 14, 2019Publication date: December 5, 2019Inventors: Trinh Hai Dang, Hsing-Lien Lin, Cheng-Yuan Tsai, Chin-Chieh Yang, Yu-Wen Liao, Wen-Ting Chu, Chia-Shiung Tsai
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Patent number: 10388865Abstract: The present disclosure, in some embodiments, relates to a resistive random access memory (RRAM) cell. The RRAM cell has a bottom electrode disposed over a lower interconnect layer and a data storage layer having a first thickness over the bottom electrode. A capping layer is disposed over the data storage layer. The capping layer has a second thickness that is in a range of between approximately 2 and approximately 3 times thicker than the first thickness. A top electrode is disposed over the capping layer and an upper interconnect layer is disposed over the top electrode.Type: GrantFiled: January 15, 2018Date of Patent: August 20, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Trinh Hai Dang, Hsing-Lien Lin, Cheng-Yuan Tsai, Chin-Chieh Yang, Yu-Wen Liao, Wen-Ting Chu, Chia-Shiung Tsai
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Patent number: 10193065Abstract: An integrated circuit or semiconductor structure of a resistive random access memory (RRAM) cell is provided. The RRAM cell includes a bottom electrode and a data storage region having a variable resistance arranged over the bottom electrode. Further, the RRAM cell includes a diffusion barrier layer arranged over the data storage region, an ion reservoir region arranged over the diffusion barrier layer, and a top electrode arranged over the ion reservoir region. A method for manufacture the integrated circuit or semiconductor structure of the RRAM cell is also provided.Type: GrantFiled: August 28, 2014Date of Patent: January 29, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Trinh Hai Dang, Hsing-Lien Lin, Chin-Wei Liang, Cheng-Yuan Tsai, Chia-Shiung Tsai
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Patent number: 10170699Abstract: The present disclosure relates to a method of forming a resistive random access memory (RRAM) cell having a reduced leakage current, and an associated apparatus. In some embodiments, the method is performed by forming a bottom electrode layer over a lower metal interconnect layer. A dielectric data storage layer having a variable resistance is formed onto the bottom electrode layer in-situ with forming at least a part of the bottom electrode layer. A top electrode layer is formed over the dielectric data storage layer. By forming the dielectric data storage layer in-situ with forming at least a part of the bottom electrode layer, leakage current, leakage current distribution and device yield of the RRAM cell are improved.Type: GrantFiled: February 15, 2017Date of Patent: January 1, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Trinh Hai Dang, Hsing-Lien Lin, Kai-Wen Cheng, Cheng-Yuan Tsai, Chia-Shiung Tsai, Ru-Liang Lee
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Publication number: 20180138402Abstract: The present disclosure, in some embodiments, relates to a resistive random access memory (RRAM) cell. The RRAM cell has a bottom electrode disposed over a lower interconnect layer and a data storage layer having a first thickness over the bottom electrode. A capping layer is disposed over the data storage layer. The capping layer has a second thickness that is in a range of between approximately 2 and approximately 3 times thicker than the first thickness. A top electrode is disposed over the capping layer and an upper interconnect layer is disposed over the top electrode.Type: ApplicationFiled: January 15, 2018Publication date: May 17, 2018Inventors: Trinh Hai Dang, Hsing-Lien Lin, Cheng-Yuan Tsai, Chin-Chieh Yang, Yu-Wen Liao, Wen-Ting Chu, Chia-Shiung Tsai
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Patent number: 9876167Abstract: The present disclosure relates to a method of forming a resistive random access memory (RRAM) cell having a good yield, and an associated apparatus. In some embodiments, the method is performed by forming a bottom electrode over a lower metal interconnect layer, and forming a variable resistance dielectric data storage layer having a first thickness onto the bottom electrode. A capping layer is formed onto the dielectric data storage layer. The capping layer has a second thickness that is in a range of between approximately 2 to approximately 3 times thicker than the first thickness. A top electrode is formed over the capping layer, and an upper metal interconnect layer is formed over the top electrode.Type: GrantFiled: January 8, 2015Date of Patent: January 23, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Trinh Hai Dang, Hsing-Lien Lin, Cheng-Yuan Tsai, Chin-Chieh Yang, Yu-Wen Liao, Wen-Ting Chu, Chia-Shiung Tsai
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Publication number: 20170162787Abstract: The present disclosure relates to a method of forming a resistive random access memory (RRAM) cell having a reduced leakage current, and an associated apparatus. In some embodiments, the method is performed by forming a bottom electrode layer over a lower metal interconnect layer. A dielectric data storage layer having a variable resistance is formed onto the bottom electrode layer in-situ with forming at least a part of the bottom electrode layer. A top electrode layer is formed over the dielectric data storage layer. By forming the dielectric data storage layer in-situ with forming at least a part of the bottom electrode layer, leakage current, leakage current distribution and device yield of the RRAM cell are improved.Type: ApplicationFiled: February 15, 2017Publication date: June 8, 2017Inventors: Trinh Hai Dang, Hsing-Lien Lin, Kai-Wen Cheng, Cheng-Yuan Tsai, Chia-Shiung Tsai, Ru-Liang Lee
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Patent number: 9577191Abstract: The present disclosure relates to a method of forming a resistive random access memory (RRAM) cell having a reduced leakage current, and an associated apparatus. In some embodiments, the method is performed by forming a bottom electrode over a lower metal interconnect layer using an atomic layer deposition (ALD) process to form at least a top portion of the bottom electrode. A dielectric data storage layer is formed onto the top portion of the bottom electrode in-situ with forming the top portion of the bottom electrode. A top electrode is formed over the dielectric data storage layer, and an upper metal interconnect layer is formed over the top electrode. By forming the top portion of the bottom electrode using an ALD process that is in-situ with the formation of the overlying dielectric data storage layer, leakage current, leakage current distribution and device yield of the RRAM cell are improved.Type: GrantFiled: April 2, 2014Date of Patent: February 21, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Trinh Hai Dang, Hsing-Lien Lin, Kai-Wen Cheng, Cheng-Yuan Tsai, Chia-Shiung Tsai, Ru-Liang Lee
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Patent number: 9431609Abstract: The present disclosure relates to a method of forming an RRAM cell having a dielectric data layer that provides good performance, device yield, and data retention, and an associated apparatus. In some embodiments, the method is performed by forming an RRAM film stack having a bottom electrode layer disposed over a semiconductor substrate, a top electrode layer, and a dielectric data storage layer disposed between the bottom electrode and the top electrode. The dielectric data storage layer has a performance enhancing layer with a hydrogen-doped oxide and a data retention layer having an aluminum oxide. The RRAM film stack is then patterned according to one or more masking layers to form a top electrode and a bottom electrode, and an upper metal interconnect layer is formed at a position electrically contacting the top electrode.Type: GrantFiled: August 14, 2014Date of Patent: August 30, 2016Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Trinh Hai Dang, Hsing-Lien Lin, Cheng-Yuan Tsai, Chia-Shiung Tsai, Ru-Liang Lee
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Publication number: 20160064664Abstract: An integrated circuit or semiconductor structure of a resistive random access memory (RRAM) cell is provided. The RRAM cell includes a bottom electrode and a data storage region having a variable resistance arranged over the bottom electrode. Further, the RRAM cell includes a diffusion barrier layer arranged over the data storage region, an ion reservoir region arranged over the diffusion barrier layer, and a top electrode arranged over the ion reservoir region. A method for manufacture the integrated circuit or semiconductor structure of the RRAM cell is also provided.Type: ApplicationFiled: August 28, 2014Publication date: March 3, 2016Inventors: Trinh Hai Dang, Hsing-Lien Lin, Chin-Wei Liang, Cheng-Yuan Tsai, Chia-Shiung Tsai
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Publication number: 20160049584Abstract: The present disclosure relates to a method of forming an RRAM cell having a dielectric data layer that provides good performance, device yield, and data retention, and an associated apparatus. In some embodiments, the method is performed by forming an RRAM film stack having a bottom electrode layer disposed over a semiconductor substrate, a top electrode layer, and a dielectric data storage layer disposed between the bottom electrode and the top electrode. The dielectric data storage layer has a performance enhancing layer with a hydrogen-doped oxide and a data retention layer having an aluminum oxide. The RRAM film stack is then patterned according to one or more masking layers to form a top electrode and a bottom electrode, and an upper metal interconnect layer is formed at a position electrically contacting the top electrode.Type: ApplicationFiled: August 14, 2014Publication date: February 18, 2016Inventors: Trinh Hai Dang, Hsing-Lien Lin, Cheng-Yuan Tsai, Chia-Shiung Tsai, Ru-Liang Lee
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Publication number: 20150287918Abstract: The present disclosure relates to a method of forming a resistive random access memory (RRAM) cell having a reduced leakage current, and an associated apparatus. In some embodiments, the method is performed by forming a bottom electrode over a lower metal interconnect layer using an atomic layer deposition (ALD) process to form at least a top portion of the bottom electrode. A dielectric data storage layer is formed onto the top portion of the bottom electrode in-situ with forming the top portion of the bottom electrode. A top electrode is formed over the dielectric data storage layer, and an upper metal interconnect layer is formed over the top electrode. By forming the top portion of the bottom electrode using an ALD process that is in-situ with the formation of the overlying dielectric data storage layer, leakage current, leakage current distribution and device yield of the RRAM cell are improved.Type: ApplicationFiled: April 2, 2014Publication date: October 8, 2015Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Trinh Hai Dang, Hsing-Lien Lin, Kai-Wen Cheng, Cheng-Yuan Tsai, Chia-Shiung Tsai, Ru-Liang Lee
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Publication number: 20150287917Abstract: The present disclosure relates to a method of forming a resistive random access memory (RRAM) cell having a good yield, and an associated apparatus. In some embodiments, the method is performed by forming a bottom electrode over a lower metal interconnect layer, and forming a variable resistance dielectric data storage layer having a first thickness onto the bottom electrode. A capping layer is formed onto the dielectric data storage layer. The capping layer has a second thickness that is in a range of between approximately 2 to approximately 3 times thicker than the first thickness. A top electrode is formed over the capping layer, and an upper metal interconnect layer is formed over the top electrode.Type: ApplicationFiled: January 8, 2015Publication date: October 8, 2015Inventors: Trinh Hai Dang, Hsing-Lien Lin, Cheng-Yuan Tsai, Chin-Chieh Yang, Yu-Wen Liao, Wen-Ting Chu, Chia-Shiung Tsai
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Patent number: 9130026Abstract: Some embodiments of the present disclosure relates to a crystalline passivation layer for effectively passivating III-N surfaces. Surface passivation of HEMTs reduces or eliminates the surface effects that can otherwise degrade device performance. The crystalline passivation layer reduces the degrading effects of surface traps and provides a good interface between a III-nitride surface and an insulator (e.g., gate dielectric formed over the passivation layer).Type: GrantFiled: September 3, 2013Date of Patent: September 8, 2015Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Han-Chin Chiu, Trinh Hai Dang, Hsing-Lien Lin, Cheng-Yuan Tsai, Chia-Shiung Tsai, Xiaomeng Chen
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Publication number: 20150060873Abstract: Some embodiments of the present disclosure relates to a crystalline passivation layer for effectively passivating III-N surfaces. Surface passivation of HEMTs reduces or eliminates the surface effects that can otherwise degrade device performance. The crystalline passivation layer reduces the degrading effects of surface traps and provides a good interface between a III-nitride surface and an insulator (e.g., gate dielectric formed over the passivation layer).Type: ApplicationFiled: September 3, 2013Publication date: March 5, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Han-Chin Chiu, Trinh Hai Dang, Hsing-Lien Lin, Cheng-Yuan Tsai, Chia-Shiung Tsai, Xiaomeng Chen