Patents by Inventor Trishul A. Chilimbi

Trishul A. Chilimbi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11803596
    Abstract: Methods and computer storage media are provided for generating entries for documents in a forward index. A document and its document identification are received, in addition to static features that are query-independent. The document is parsed into tokens to form a token stream corresponding to the document. Relevant data used to calculate rankings of document is identified and a position of the data is determined. The entry is then generated from the document identification, the token stream of the document, the static features, and the positional information of the relevant data. The entry is stored in the forward index.
    Type: Grant
    Filed: October 1, 2019
    Date of Patent: October 31, 2023
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Knut Magne Risvik, Michael Hopcroft, John G. Bennett, Karthik Kalyanaraman, Trishul Chilimbi, Chad P. Walters, Vishesh Parikh, Jan Otto Pedersen
  • Publication number: 20200192948
    Abstract: Methods and computer storage media are provided for generating entries for documents in a forward index. A document and its document identification are received, in addition to static features that are query-independent. The document is parsed into tokens to form a token stream corresponding to the document. Relevant data used to calculate rankings of document is identified and a position of the data is determined. The entry is then generated from the document identification, the token stream of the document, the static features, and the positional information of the relevant data. The entry is stored in the forward index.
    Type: Application
    Filed: October 1, 2019
    Publication date: June 18, 2020
    Inventors: KNUT MAGNE RISVIK, MICHAEL HOPCROFT, JOHN G. BENNETT, KARTHIK KALYANARAMAN, TRISHUL CHILIMBI, CHAD P. WALTERS, VISHESH PARIKH, JAN OTTO PEDERSEN
  • Patent number: 10686869
    Abstract: A performance investigation tool (PIT) is described herein for investigating the performance of a distributed processing system (DPS). The PIT operates by first receiving input information that describes a graph processing task to be executed using a plurality of computing units. The PIT then determines, based on the input information, at least one time-based performance measure that describes the performance of a DPS that is capable of performing the graphical task. More specifically, the PIT can operate in a manual mode to explore the behavior of a specified DPS, or in an automatic mode to find an optimal DPS from within a search space of candidate DPSs. A configuration system may then be used to construct a selected DPS, using the plurality of computing units. In one case, the graph processing task involves training a deep neural network model having a plurality of layers.
    Type: Grant
    Filed: September 29, 2014
    Date of Patent: June 16, 2020
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Trishul Chilimbi, Yutaka Suzue, Johnson T. Apacible, Karthik Kalyanaraman, Olatunji Ruwase, Yuxiong He, Feng Yan
  • Patent number: 10592252
    Abstract: Efficient instruction processing for sparse data includes extensions to a processor pipeline to identify zero-optimizable instructions that include at least one zero input operand, and bypass the execute stage of the processor pipeline, determining the result of the operation without executing the instruction. When possible, the extensions also bypass the writeback stage of the processor pipeline.
    Type: Grant
    Filed: December 31, 2015
    Date of Patent: March 17, 2020
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Trishul A. Chilimbi, Olatunji Ruwase, Vivek Seshadri
  • Patent number: 10459727
    Abstract: Loop code processor optimizations are implemented as a loop optimizer extension to a processor pipeline. The loop optimizer generates optimized code associated with code loops that include at least one zero-optimizable instruction. The loop optimizer may generate multiple versions of optimized code associated with a particular code loop, where each of the multiple version of optimized code has a different associated condition under which the optimized code can be safely executed.
    Type: Grant
    Filed: December 31, 2015
    Date of Patent: October 29, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Trishul A Chilimbi, Olatunji Ruwase, Vivek Seshadri
  • Patent number: 10437892
    Abstract: Methods and computer storage media are provided for generating entries for documents in a forward index. A document and its document identification are received, in addition to static features that are query-independent. The document is parsed into tokens to form a token stream corresponding to the document. Relevant data used to calculate rankings of document is identified and a position of the data is determined. The entry is then generated from the document identification, the token stream of the document, the static features, and the positional information of the relevant data. The entry is stored in the forward index.
    Type: Grant
    Filed: July 8, 2014
    Date of Patent: October 8, 2019
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Knut Magne Risvik, Michael Hopcroft, John G. Bennett, Karthik Kalyanaraman, Trishul Chilimbi, Chad P. Walters, Vishesh Parikh, Jan Otto Pedersen
  • Publication number: 20170192896
    Abstract: A zero cache memory system extension includes a zero cache to store cache tags associated with zero cache lines, while a corresponding data cache stores cache tags and data bytes associated with non-zero cache lines. As non-zero data is written to the cache, cache lines may be moved from the zero cache to the data cache. Similarly, as zero data is written to the cache, cache lines may be moved from the data cache to the zero cache.
    Type: Application
    Filed: December 31, 2015
    Publication date: July 6, 2017
    Inventors: Trishul A Chilimbi, Olatunji Ruwase, Vivek Seshadri
  • Publication number: 20170192787
    Abstract: Loop code processor optimizations are implemented as a loop optimizer extension to a processor pipeline. The loop optimizer generates optimized code associated with code loops that include at least one zero-optimizable instruction. The loop optimizer may generate multiple versions of optimized code associated with a particular code loop, where each of the multiple version of optimized code has a different associated condition under which the optimized code can be safely executed.
    Type: Application
    Filed: December 31, 2015
    Publication date: July 6, 2017
    Inventors: Trishul A. Chilimbi, Olatunji Ruwase, Vivek Seshadri
  • Publication number: 20170193361
    Abstract: A neural network training tool selects from a plurality of parallelizing techniques and selects from a plurality of forward-propagation computation techniques. The neural network training tool performs a forward-propagation phase to train a neural network using the selected parallelizing technique and the selected forward-propagation computation technique based on one or more inputs. Additionally, the neural network training tool selects from a plurality computation techniques and from a plurality of parallelizing techniques for a backward-propagation phase. The neural network training tool performs a backward-propagation phase of training the neural network using the selected backward-propagation parallelizing technique and the selected backward-propagation computation technique to generate error gradients and weight deltas and to update weights associated with one or more layers of the neural network.
    Type: Application
    Filed: December 31, 2015
    Publication date: July 6, 2017
    Inventors: Trishul A. Chilimbi, Olatunji Ruwase, Samyam Rajbhandari, Michael Carbin, Yuxiong He
  • Publication number: 20170192793
    Abstract: Efficient instruction processing for sparse data includes extensions to a processor pipeline to identify zero-optimizable instructions that include at least one zero input operand, and bypass the execute stage of the processor pipeline, determining the result of the operation without executing the instruction. When possible, the extensions also bypass the writeback stage of the processor pipeline.
    Type: Application
    Filed: December 31, 2015
    Publication date: July 6, 2017
    Inventors: Trishul A. Chilimbi, Olatunji Ruwase, Vivek Seshadri
  • Publication number: 20170083553
    Abstract: A search index includes tiered posting lists. Each posting list in the search index corresponds with a different atom and includes a list of documents containing the particular document. Additionally, a rank is stored with each document listed in a posting list for a given atom representing the relevance of the atom to the context of each document. At least some of the posting lists in the search index are tiered. A tiered posting list is divided into a number of tiers with the tiers being ordered by document while each tier is internally ordered by document. Employing tiered posting lists within the search index allows a search engine to evaluate search queries in a manner that allows for a number of efficiencies and precise stopping.
    Type: Application
    Filed: November 30, 2016
    Publication date: March 23, 2017
    Inventors: Knut Magne Risvik, Michael Hopcroft, John G. Bennett, Karthik Kalyanaraman, Trishul Chilimbi
  • Patent number: 9529908
    Abstract: A search index includes tiered posting lists. Each posting list in the search index corresponds with a different atom and includes a list of documents containing the particular document. Additionally, a rank is stored with each document listed in a posting list for a given atom representing the relevance of the atom to the context of each document. At least some of the posting lists in the search index are tiered. A tiered posting list is divided into a number of tiers with the tiers being ordered by document while each tier is internally ordered by document. Employing tiered posting lists within the search index allows a search engine to evaluate search queries in a manner that allows for a number of efficiencies and precise stopping.
    Type: Grant
    Filed: November 22, 2010
    Date of Patent: December 27, 2016
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Knut Magne Risvik, Michael Hopcroft, John G. Bennett, Karthik Kalyanaraman, Trishul Chilimbi
  • Patent number: 9424351
    Abstract: Methods and systems are provided for using a hybrid-distribution system to identify relevant documents based on a search query. A group of documents is assigned to a particular segment. The group of documents is indexed both by atom and by document to form a reverse index and a forward index. Both indexes are divided amongst each node in that segment so that each node is responsible for storing and accessing a different portion of both the reverse and forward indexes. The reverse index portion is accessed on each of a first set of nodes to identify a first set of documents that is relevant to a particular search query. Document identifications associated with the first set of documents are used to identify a second set of nodes that access their forward index portions to limit the number of relevant documents to a second set of documents.
    Type: Grant
    Filed: November 22, 2010
    Date of Patent: August 23, 2016
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Knut Magne Risvik, Michael Hopcroft, John Bennett, Karthik Kalyanaraman, Trishul Chilimbi, Chad P. Walters, Vishesh Parikh, Jan Otto Pedersen
  • Patent number: 9342582
    Abstract: Methods are provided for populating search indexes with atoms identified in documents. Documents that are to be indexed are identified, and for each document, atoms are identified and are categorized as unigrams, n-grams, and n-tuples. A list of atom/document pairs is generated such that an information metric can be computed for each pair. An information metric represents a ranking of the atom in relation to the particular document. Based on the information metric, some atom/document pairs are discarded and others are indexed.
    Type: Grant
    Filed: March 10, 2011
    Date of Patent: May 17, 2016
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Knut Magne Risvik, Mike Hopcroft, John G. Bennett, Karthik Kalyanaraman, Trishul Chilimbi
  • Patent number: 9329876
    Abstract: The described implementations relate to resource aware programming. In one case a program is obtained that is configured to perform a task in accordance with one or more quantitative metrics. An approximate version can be generated from the program. The approximate version is configured to perform the task in a manner that satisfies the one or more quantitative metrics while using fewer computer resources than the program.
    Type: Grant
    Filed: May 20, 2009
    Date of Patent: May 3, 2016
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Trishul A. Chilimbi, Woongki Baek
  • Publication number: 20160092765
    Abstract: A performance investigation tool (PIT) is described herein for investigating the performance of a distributed processing system (DPS). The PIT operates by first receiving input information that describes a graph processing task to be executed using a plurality of computing units. The PIT then determines, based on the input information, at least one time-based performance measure that describes the performance of a DPS that is capable of performing the graphical task. More specifically, the PIT can operate in a manual mode to explore the behavior of a specified DPS, or in an automatic mode to find an optimal DPS from within a search space of candidate DPSs. A configuration system may then be used to construct a selected DPS, using the plurality of computing units. In one case, the graph processing task involves training a deep neural network model having a plurality of layers.
    Type: Application
    Filed: September 29, 2014
    Publication date: March 31, 2016
    Inventors: Trishul Chilimbi, Yutaka Suzue, Johnson T. Apacible, Karthik Kalyanaraman, Olatunji Ruwase, Yuxiong He, Feng Yan
  • Patent number: 9195745
    Abstract: A preliminary segment root and a final segment root are selected for each segment. Each time a search query is received, a set of nodes in each segment that will be used to resolve the search query is identified. A preliminary segment root is selected from the set of nodes. Based on statistical data from each node in the set of nodes indicating each node's capability to act as a final segment root that assembles query-execution data, the preliminary segment root algorithmically selects the final segment root. The other nodes in the set of nodes are notified regarding the identity of the final segment root.
    Type: Grant
    Filed: March 25, 2011
    Date of Patent: November 24, 2015
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Knut Magne Risvik, Michael Hopcroft, Karthik Kalyanaraman, Trishul Chilimbi, Henry Setiawan, Christopher W. Anderson
  • Publication number: 20150324690
    Abstract: Training large neural network models by providing training input to model training machines organized as multiple replicas that asynchronously update a shared model via a global parameter server is described herein. In at least one embodiment, a system including a model module storing a portion of a model and a deep learning training module that communicates with the model module are configured for asynchronously sending updates to shared parameters associated with the model. The techniques herein describe receiving and processing a batch of data items to calculate updates. Replicas of training machines communicate asynchronously with a global parameter server to provide updates to a shared model and return updated weight values. The model may be modified to reflect the updated weight values. The techniques described herein include computation and communication optimizations that improve system efficiency and scaling of large neural networks.
    Type: Application
    Filed: September 22, 2014
    Publication date: November 12, 2015
    Inventors: Trishul A. Chilimbi, Yutaka Suzue, Johnson R. Apacible, Karthik Kalyanaraman
  • Patent number: 8959442
    Abstract: A “Memory Allocation Visualizer” provides a dynamic visualization that animates memory allocation event trace information over a time period of execution of a program. Consequently, the Memory Allocation Visualizer provides a visualization and understanding of a program's memory system behavior. Various modes of display with custom color mappings and zooming allow the user to see how heaps are used over time (e.g., by allocation type, age, size, thread id, etc.). Custom displays also allow the user to detect potential memory leaks and fragmentation problems. Composable filters enable the user to focus on specific issues. Various techniques are used to enable processing of a very large numbers of trace events while enabling rapid response to visualization view changes.
    Type: Grant
    Filed: June 11, 2010
    Date of Patent: February 17, 2015
    Assignee: Microsoft Corporation
    Inventors: Trishul A. Chilimbi, Bongshin Lee, George G. Robertson
  • Patent number: 8914781
    Abstract: Described is predicting cache locality in a multicore/multithreaded processing environment including when threads share cache data in a non-uniform interleaving manner. Thread execution traces are analyzed to compute a set of per-thread parameters that can then be used to predict cache miss rates for other cache sizes. In one aspect, a model is based upon a probability that the cache reuse distance will increase because of accesses by other threads, and another probability that the reuse distance will decrease because of intercept accesses by other threads to shared data blocks. Estimates of the number of shared data blocks, possibly shared data blocks and private data blocks are used in the computations.
    Type: Grant
    Filed: October 24, 2008
    Date of Patent: December 16, 2014
    Assignee: Microsoft Corporation
    Inventors: Trishul A. Chilimbi, Chen Ding