Patents by Inventor Tristan Ma
Tristan Ma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10269663Abstract: An apparatus of a wafer processing apparatus includes at least one memory and logic, at least a portion of which is implemented in circuitry of the wafer processing apparatus including at least one processor coupled to the at least one memory. The logic may provide a 3D model of a surface of a wafer, the wafer defining a wafer plane; and modify a surface feature in a Z-direction along the surface of the wafer based on at least one of: an X-critical dimension (CD) extending along an X-direction of the wafer plane, and a Y-CD extending along a Y direction of the wafer plane.Type: GrantFiled: January 6, 2017Date of Patent: April 23, 2019Assignee: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.Inventors: Morgan D. Evans, Tristan Ma, Kevin Anglin, Motoya Okazaki, Johannes M. van Meer
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Patent number: 10204909Abstract: Provided herein are approaches for forming a gate oxide layer for a DRAM device, the method including providing a finned substrate having a recess formed therein, and performing an ion implant into a sidewall surface of the recess to form a gate oxide layer having a non-uniform thickness, wherein a thickness of the gate oxide layer at a top section of the sidewall surface is greater than a thickness of the gate oxide layer at a bottom section of the sidewall surface. In some approaches, the ion implant is provided as a series of ion implants at multiple different implant angles, varied along with an ion implantation energy and/or an ion dose to increase the thickness of the gate oxide of the top section of the sidewall surface. In some approaches, the finned substrate is also exposed to a plasma, either during or after, the ion implantation.Type: GrantFiled: December 22, 2015Date of Patent: February 12, 2019Assignee: Varian Semiconductor Equipment Associates, Inc.Inventors: Simon Ruffell, Arvind Kumar, Tristan Ma, Kyu-Ha Shim, John Hautala, Steven Sherman
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Publication number: 20180197796Abstract: An apparatus of a wafer processing apparatus includes at least one memory and logic, at least a portion of which is implemented in circuitry of the wafer processing apparatus including at least one processor coupled to the at least one memory. The logic may provide a 3D model of a surface of a wafer, the wafer defining a wafer plane; and modify a surface feature in a Z-direction along the surface of the wafer based on at least one of: an X-critical dimension (CD) extending along an X-direction of the wafer plane, and a Y-CD extending along a Y direction of the wafer plane.Type: ApplicationFiled: January 6, 2017Publication date: July 12, 2018Inventors: Morgan D. Evans, Tristan Ma, Kevin Anglin, Motoya Okazaki, Johannes M. van Meer
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Publication number: 20180174843Abstract: A method of etching a workpiece comprising two or more materials is disclosed. The method involves using physical sputtering as the etching method where the processing parameters of the sputtering process are tuned to achieve a desired etch rate selectivity. The method includes determining the etch rate of each material disposed on the workpiece as a function of various processing parameters, such as ion species, ion energy, incidence angle and temperature. Once the relationship between etch rate and these parameters is determined for each material, a set of values for these processing parameters may be chosen to achieve the desired etch rate selectivity.Type: ApplicationFiled: December 16, 2016Publication date: June 21, 2018Inventors: Kevin Anglin, Tristan Ma, Morgan D. Evans, John Hautala, Heyun Yin
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Patent number: 10002764Abstract: A method of etching a workpiece comprising two or more materials is disclosed. The method involves using physical sputtering as the etching method where the processing parameters of the sputtering process are tuned to achieve a desired etch rate selectivity. The method includes determining the etch rate of each material disposed on the workpiece as a function of various processing parameters, such as ion species, ion energy, incidence angle and temperature. Once the relationship between etch rate and these parameters is determined for each material, a set of values for these processing parameters may be chosen to achieve the desired etch rate selectivity.Type: GrantFiled: December 16, 2016Date of Patent: June 19, 2018Assignee: Varian Semiconductor Equipment Associates, Inc.Inventors: Kevin Anglin, Tristan Ma, Morgan D. Evans, John Hautala, Heyun Yin
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Patent number: 9929015Abstract: In one embodiment, a processing apparatus may include a process chamber configured to house a substrate and a hybrid source assembly that includes a gas channel coupled to a molecular source; and a plasma chamber configured to generate a plasma and isolated from the gas channel. The processing apparatus may also include an extraction assembly disposed between the hybrid source assembly and process chamber, coupled to the gas channel and plasma chamber, and configured to direct an ion beam to a substrate, the ion beam comprising angled ions wherein the angled ions form a non-zero angle with respect to a perpendicular to a substrate plane; and configured to direct a molecular beam comprising molecular species received from the gas channel to the substrate.Type: GrantFiled: July 21, 2014Date of Patent: March 27, 2018Assignee: Varian Semiconductor Equipment Associates, Inc.Inventors: Thomas R. Omstead, Simon Ruffell, Tristan Ma, Ethan A. Wright, John Hautala
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Patent number: 9885957Abstract: Provided herein are approaches for patterning a semiconductor device. Exemplary approaches include providing a set of photoresist patterning features atop a substrate, the set of patterning features having a surface roughness characterized by a set of protrusions and a set of indentations. The approaches further include implanting first ions into a sidewall surface of the set of photoresist patterning features to form a film layer having a non-uniform thickness along the sidewall surface, wherein a thickness of the film layer formed over the indentations is greater than a thickness of the film layer formed over the protrusions. The approaches further include sputtering the sidewall surface of the photoresist patterning features following the formation of the film layer to modify a portion of the film layer and/or the set of protrusions, wherein the sputtering includes directing second ions to photoresist patterning features at an angle with the sidewall surface.Type: GrantFiled: April 21, 2017Date of Patent: February 6, 2018Assignee: Varian Semiconductor Equipment Associates, Inc.Inventors: Maureen K. Petterson, Tristan Ma, John Hautala
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Publication number: 20170219926Abstract: Provided herein are approaches for patterning a semiconductor device. Exemplary approaches include providing a set of photoresist patterning features atop a substrate, the set of patterning features having a surface roughness characterized by a set of protrusions and a set of indentations. The approaches further include implanting first ions into a sidewall surface of the set of photoresist patterning features to form a film layer having a non-uniform thickness along the sidewall surface, wherein a thickness of the film layer formed over the indentations is greater than a thickness of the film layer formed over the protrusions. The approaches further include sputtering the sidewall surface of the photoresist patterning features following the formation of the film layer to modify a portion of the film layer and/or the set of protrusions, wherein the sputtering includes directing second ions to photoresist patterning features at an angle with the sidewall surface.Type: ApplicationFiled: April 21, 2017Publication date: August 3, 2017Inventors: Maureen K. Petterson, Tristan Ma, John Hautala
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Publication number: 20170179133Abstract: Provided herein are approaches for forming a gate oxide layer for a DRAM device, the method including providing a finned substrate having a recess formed therein, and performing an ion implant into a sidewall surface of the recess to form a gate oxide layer having a non-uniform thickness, wherein a thickness of the gate oxide layer at a top section of the sidewall surface is greater than a thickness of the gate oxide layer at a bottom section of the sidewall surface. In some approaches, the ion implant is provided as a series of ion implants at multiple different implant angles, varied along with an ion implantation energy and/or an ion dose to increase the thickness of the gate oxide of the top section of the sidewall surface. In some approaches, the finned substrate is also exposed to a plasma, either during or after, the ion implantation.Type: ApplicationFiled: December 22, 2015Publication date: June 22, 2017Inventors: Simon Ruffell, Arvind Kumar, Tristan Ma, Kyu-Ha Shim, John Hautala, Steven Sherman
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Patent number: 9659784Abstract: Provided herein are approaches for patterning a semiconductor device. Exemplary approaches include providing a set of photoresist patterning features atop a substrate, the set of patterning features having a surface roughness characterized by a set of protrusions and a set of indentations. The approaches further include implanting first ions into a sidewall surface of the set of photoresist patterning features to form a film layer having a non-uniform thickness along the sidewall surface, wherein a thickness of the film layer formed over the indentations is greater than a thickness of the film layer formed over the protrusions. The approaches further include sputtering the sidewall surface of the photoresist patterning features following the formation of the film layer to modify a portion of the film layer and/or the set of protrusions, wherein the sputtering includes directing second ions to photoresist patterning features at an angle with the sidewall surface.Type: GrantFiled: December 22, 2015Date of Patent: May 23, 2017Assignee: Varian Semiconductor Equipment Associates, Inc.Inventors: Maureen K. Petterson, Tristan Ma, John Hautala
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Publication number: 20160379844Abstract: In one embodiment, a method for etching a copper layer disposed on a substrate includes directing reactive ions to the substrate when a mask that defines an exposed area and protected area is disposed on the copper layer, wherein an altered layer is generated in the exposed area comprising a chemically reactive material; and exposing the copper layer to a molecular species that is effective to react with the chemically reactive material so as to remove the altered layer.Type: ApplicationFiled: September 13, 2016Publication date: December 29, 2016Inventors: Thomas R. Omstead, Tristan MA, Ludovic Godet
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Patent number: 9460961Abstract: In one embodiment, a method for etching a copper layer disposed on a substrate includes directing reactive ions to the substrate when a mask that defines an exposed area and protected area is disposed on the copper layer, wherein an altered layer is generated in the exposed area comprising a chemically reactive material; and exposing the copper layer to a molecular species that is effective to react with the chemically reactive material so as to remove the altered layer.Type: GrantFiled: August 5, 2014Date of Patent: October 4, 2016Assignee: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.Inventors: Thomas R. Omstead, Tristan Ma, Ludovic Godet
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Patent number: 9435038Abstract: An improved method of etching a metal substrate is described. After a mask layer is applied to the metal substrate, an ion implantation process is performed which implants ions, such as oxygen ions, into the exposed regions of the metal substrate. This implantation creates regions of metal oxide, which may be more susceptible to etching. Afterwards, the exposed regions of metal oxide are subjected to an etching process. This process may be through vaporization or may be a wet etch process. In some embodiments, the etchant is selected so that the metal oxide binds with the etchant to form a volatile compound, which stays in the vapor or gaseous state. This may reduce the unwanted deposition of the metal to other surfaces. These ion implantation and etching processes may be repeated a plurality of times to create a recessed feature of the desired depth.Type: GrantFiled: August 29, 2014Date of Patent: September 6, 2016Assignee: Varian Semiconductor Equipment Associates, Inc.Inventors: Thomas Omstead, William Davis Lee, Tristan Ma
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Patent number: 9396965Abstract: In one embodiment, a method for etching a metal layer on a substrate may include providing a hydrogen-containing gas and an impurity gas to a plasma chamber; generating a plasma from the hydrogen-containing gas and the impurity gas in the plasma chamber, the plasma comprising hydrogen-containing ions; providing gaseous species from the plasma chamber to the substrate, wherein the providing the gaseous species comprises directing an ion beam comprising the hydrogen-containing ions formed from the plasma through an extraction aperture of an extraction plate disposed between the substrate and the plasma.Type: GrantFiled: August 5, 2014Date of Patent: July 19, 2016Assignee: Varian Semiconductor Equipment Associates, Inc.Inventors: Tristan Ma, Ludovic Godet, Thomas R. Omstead
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Patent number: 9385219Abstract: Methods for forming fin structures with desired materials formed on different locations of the fin structure using a selective deposition process for fin field effect transistors (FinFETs) are provided. In one embodiment, a method of forming a structure with desired materials on a substrate includes depositing a first material on a substrate having a three-dimensional (3D) structure formed thereon while performing an implantation process to dope a first region of the 3D structure. The first material may be removed and a second material may be deposited on the 3D structure. The second material may selectively grow on a second region of the 3D structure.Type: GrantFiled: June 29, 2015Date of Patent: July 5, 2016Assignee: APPLIED MATERIALS, INC.Inventors: Ellie Y. Yieh, Srinivas D. Nemani, Ludovic Godet, Yin Fan, Tristan Ma
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Patent number: 9377692Abstract: Methods and apparatuses for minimizing line edge/width roughness in lines formed by photolithography are provided. The random diffusion of acid generated by a photoacid generator during a lithography process contributes to line edge/width roughness. Methods disclosed herein apply an electric field and/or a magnetic field during photolithography processes. The field application controls the diffusion of the acids generated by the photoacid generator along the line and spacing direction, preventing the line edge/width roughness that results from random diffusion. Apparatuses for carrying out the aforementioned methods are also disclosed herein.Type: GrantFiled: June 10, 2014Date of Patent: June 28, 2016Assignee: APPLIED MATERIALS, INC.Inventors: Peng Xie, Ludovic Godet, Tristan Ma, Joseph C. Olson, Christopher Bencher
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Patent number: 9336998Abstract: In one embodiment a method of etching a substrate includes directing a first ion beam to the substrate through an extraction plate of a processing apparatus using a first set of control settings of the processing apparatus. The method may further include detecting a signal from the substrate that indicates a change in material being etched by the first ion beam from a first material to a second material, adjusting control settings of the processing apparatus to a second set of control settings different from the first set of control settings based on the second material, and directing a second ion beam to the substrate through the extraction plate using the second set of control settings.Type: GrantFiled: May 9, 2014Date of Patent: May 10, 2016Assignee: Varian Semiconductor Equipment Associates, Inc.Inventors: Ludovic Godet, Daniel Distaso, Nini Munoz, Tristan Ma, Yu Liu
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Publication number: 20160060767Abstract: An improved method of etching a metal substrate is described. After a mask layer is applied to the metal substrate, an ion implantation process is performed which implants ions, such as oxygen ions, into the exposed regions of the metal substrate. This implantation creates regions of metal oxide, which may be more susceptible to etching. Afterwards, the exposed regions of metal oxide are subjected to an etching process. This process may be through vaporization or may be a wet etch process. In some embodiments, the etchant is selected so that the metal oxide binds with the etchant to form a volatile compound, which stays in the vapor or gaseous state. This may reduce the unwanted deposition of the metal to other surfaces. These ion implantation and etching processes may be repeated a plurality of times to create a recessed feature of the desired depth.Type: ApplicationFiled: August 29, 2014Publication date: March 3, 2016Inventors: Thomas Omstead, William Davis Lee, Tristan Ma
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Patent number: 9268228Abstract: Various techniques for patterning a substrate are disclosed. Specifically, implantation of the first species into an anti-reflective coating layer is contemplated to reduce stress in the layer that may be generated during the exposure stage or development stage. During these steps, the resist layer or the resist structure may under mechanical changes (e.g. shrinkage) while it is in contact with the anti-reflective layer. Such changes may introduce stress in the anti-reflective layer, which may contribute to excessive line edge roughness (LER) or line width roughness (LWR). By implanting the first species before, during, or after these steps, the stress in the anti-reflective layer may be avoided or compensated, and excessive LER or LWR may be avoided or reduced.Type: GrantFiled: February 10, 2014Date of Patent: February 23, 2016Assignee: Varian Semiconductor Equipment Associates, Inc.Inventors: Ludovic Godet, Tristan Ma
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Publication number: 20160042922Abstract: In one embodiment, a method for etching a copper layer disposed on a substrate includes directing reactive ions to the substrate when a mask that defines an exposed area and protected area is disposed on the copper layer, wherein an altered layer is generated in the exposed area comprising a chemically reactive material; and exposing the copper layer to a molecular species that is effective to react with the chemically reactive material so as to remove the altered layer.Type: ApplicationFiled: August 5, 2014Publication date: February 11, 2016Inventors: Thomas R. Omstead, Tristan MA, Ludovic Godet