Patents by Inventor Trong Huynh Bao
Trong Huynh Bao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11832525Abstract: The material layer stack includes first and second magnetic tunnel junctions and a first top electrode formed on a top face of the stack. A shoulder is formed on a lateral face of the stack and divides the stack into a lower portion and an upper portion. A tunnel barrier of the first magnetic tunnel junction is comprised by the lower stack portion and a tunnel barrier of the second magnetic tunnel junction by the upper stack portion. A second top electrode is formed on the shoulder. Each magnetic tunnel junction is adapted to store a bit as a reconfigurable magnetoresistance of its magnetic electrodes. Preferably, a bottom face of the stack is connected to a conductor supporting current induced magnetic polarization switching for the first magnetic tunnel junction by spin-orbit torque. Magnetic polarization switching for the second magnetic tunnel junction is preferably achieved by spin-transfer torque.Type: GrantFiled: December 11, 2020Date of Patent: November 28, 2023Assignees: IMEC vzw, Katholieke Universiteit LeuvenInventors: Mohit Gupta, Trong Huynh Bao
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Patent number: 11527709Abstract: The disclosed technology relates to a multibit memory cell. In one aspect, the multibit memory cell includes a plurality of spin-orbit torque (SOT) tracks, plurality of magnetic tunnel junctions (MTJs), an electrically conductive path connecting a first MTJ and a second MTJ together, and a plurality of terminals. The plurality of terminals can be configured to provide a first SOT write current to the first MTJ, a second SOT write current to the second MTJ, and at least one of: the second SOT write current to a third MTJ, a third SOT write current to the third MTJ, and a spin transfer torque (STT) write current through the third MTJ. The junction resistances of the various MTJs are such that a combined multibit memory state of the MTJs is readable by a read current through all the MTJs in series.Type: GrantFiled: September 21, 2020Date of Patent: December 13, 2022Assignees: IMEC vzw, Katholieke Universiteit LeuvenInventors: Mohit Gupta, Trong Huynh Bao
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Patent number: 11227645Abstract: According to an example embodiment an MTJ unit is provided. The MTJ unit includes: a first MTJ comprising a first free layer, a first tunnel barrier layer and a first reference layer. The first MTJ is switchable between a parallel state and an anti-parallel state through spin-torque transfer (STT). The MTJ unit comprises a second MTJ arranged above the first MTJ and comprising, a second reference layer, a second tunnel barrier layer and a second free layer. The second MTJ is switchable between a parallel state and an anti-parallel state through STT. The MTJ unit comprises a pinning layer arranged between the first reference layer and the second reference layer and configured to fix a magnetization direction of the first reference layer and the second reference layer.Type: GrantFiled: December 6, 2019Date of Patent: January 18, 2022Assignee: IMEC VZWInventors: Sushil Sakhare, Manu Komalan Perumkunnil, Johan Swerts, Gouri Sankar Kar, Trong Huynh Bao
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Patent number: 11217488Abstract: The disclosed technology generally relates to semiconductor devices and methods of forming the same. In one aspect, a method of forming a semiconductor device having vertical channel field-effect transistor (FET) devices comprises forming on a substrate, a plurality of semiconductor structures protruding vertically from a lower source/drain semiconductor layer of the substrate. The semiconductor structures can be arranged in an array having a plurality of rows and columns. The method can include etching metal line trenches between at least a subset of the rows and forming metal lines in the metal line trenches to contact the lower source/drain layer. The method can also include forming gate structures at least partly enclosing semiconductor structure channel portions located above the lower source/drain layer and forming upper source/drain metal contacts on semiconductor structure upper source/drain portions located above the channel portions.Type: GrantFiled: March 31, 2020Date of Patent: January 4, 2022Assignee: IMEC zvwInventors: Anabela Veloso, Trong Huynh Bao, Raf Appeltans
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Patent number: 11201093Abstract: A method of fabricating a semiconductor device is disclosed. In one aspect, the method includes forming, in a vertical channel field-effect transistor (FET) device region, a vertical channel FET device including a first semiconductor structure including a lower source/drain portion, an upper source/drain portion, a first channel portion extending vertically and intermediate the source/drain portions and a gate structure extending along the channel portion and, in a horizontal channel FET device region, a horizontal channel FET device comprising a second semiconductor structure including a first source/drain portion, a second source/drain portion, a second channel portion extending horizontally and intermediate the source/drain portions, and a gate structure extending across the channel portion.Type: GrantFiled: March 31, 2020Date of Patent: December 14, 2021Assignee: IMEC vzwInventors: Anabela Veloso, Trong Huynh Bao, Julien Ryckaert, Raf Appeltans
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Patent number: 11087837Abstract: A circuit cell for a memory device or a logic device comprises: (i) first and a second logic gates having respective output nodes; and (ii) first and second memory units, each comprising (a) first and second terminals and (b) a resistive memory element and a bipolar selector connected in series between the first and second terminals, wherein the first terminals of the first and second memory units are connected to the output nodes of the first and second logic gates, respectively, wherein the resistive memory elements are configured to be switchable between first and second resistance states, and wherein in response to a switching current and the bipolar selectors are configured to be conducting in response to an absolute value of a voltage difference across the bipolar selectors exceeding a threshold voltage of the bipolar selectors and non-conducting in response to the absolute value being lower than the threshold.Type: GrantFiled: December 26, 2019Date of Patent: August 10, 2021Assignee: IMEC vzwInventors: Trong Huynh Bao, Sushil Sakhare
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Publication number: 20210193912Abstract: A material layer stack, a non-volatile memory device comprising the stack, and arrays thereof are described. The material layer stack comprises first and second magnetic tunnel junctions and a first top electrode formed on a top face of the stack. A shoulder is formed on a lateral face of the stack and divides the stack into a lower portion and an upper portion, wherein a tunnel barrier of the first magnetic tunnel junction is comprised by the lower stack portion and a tunnel barrier of the second magnetic tunnel junction by the upper stack portion. A second top electrode is formed on the shoulder. Each magnetic tunnel junction is adapted to store a bit as a reconfigurable magnetoresistance of its magnetic electrodes.Type: ApplicationFiled: December 11, 2020Publication date: June 24, 2021Inventors: Mohit Gupta, Trong Huynh Bao
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Patent number: 11018235Abstract: The disclosed technology generally relates to semiconductor devices, and more particularly to semiconductor devices having a stacked arrangement, and further relates to methods of fabricating such devices. In one aspect, a semiconductor device comprises a first memory device and a second memory device formed over a substrate and at least partly stacked in a vertical direction. Each of the first and second memory devices has a plurality of vertical transistors, wherein each vertical transistor has a vertical channel extending in the vertical direction.Type: GrantFiled: November 11, 2016Date of Patent: May 25, 2021Assignees: IMEC vzw, Vrije Universiteit BrusselInventors: Trong Huynh Bao, Anabela Veloso, Julien Ryckaert
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Publication number: 20210098694Abstract: The disclosed technology relates to a multibit memory cell. In one aspect, the multibit memory cell includes a plurality of spin-orbit torque (SOT) tracks, including at least a first SOT track and a second SOT track separate from the first SOT track. The cell further includes a plurality of magnetic tunnel junctions (MTJs), including at least a first MTJ arranged on the first SOT track, and a second MTJ and a third MTJ arranged on the second SOT track. The cell further includes an electrically conductive path connecting the first MTJ and the second MTJ together, and a plurality of terminals, of which some may be optional. The plurality of terminals can be configured to provide a first SOT write current to the first MTJ, a second SOT write current to the second MTJ, and at least one of: the second SOT write current to the third MTJ, a third SOT write current to the third MTJ, and an spin transfer torque (STT) write current through the third MTJ.Type: ApplicationFiled: September 21, 2020Publication date: April 1, 2021Inventors: Mohit Gupta, Trong Huynh Bao
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Publication number: 20200312726Abstract: A method of fabricating a semiconductor device is disclosed. In one aspect, the method includes forming, in a vertical channel field-effect transistor (FET) device region, a vertical channel FET device including a first semiconductor structure including a lower source/drain portion, an upper source/drain portion, a first channel portion extending vertically and intermediate the source/drain portions and a gate structure extending along the channel portion and, in a horizontal channel FET device region, a horizontal channel FET device comprising a second semiconductor structure including a first source/drain portion, a second source/drain portion, a second channel portion extending horizontally and intermediate the source/drain portions, and a gate structure extending across the channel portion.Type: ApplicationFiled: March 31, 2020Publication date: October 1, 2020Inventors: Anabela Veloso, Trong Huynh Bao, Julien Ryckaert, Raf Appeltans
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Publication number: 20200312721Abstract: The disclosed technology generally relates to semiconductor devices and methods of forming the same. In one aspect, a method of forming a semiconductor device having vertical channel field-effect transistor (FET) devices comprises forming on a substrate, a plurality of semiconductor structures protruding vertically from a lower source/drain semiconductor layer of the substrate. The semiconductor structures can be arranged in an array having a plurality of rows and columns. The method can include etching metal line trenches between at least a subset of the rows and forming metal lines in the metal line trenches to contact the lower source/drain layer. The method can also include forming gate structures at least partly enclosing semiconductor structure channel portions located above the lower source/drain layer and forming upper source/drain metal contacts on semiconductor structure upper source/drain portions located above the channel portions.Type: ApplicationFiled: March 31, 2020Publication date: October 1, 2020Inventors: Anabela VELOSO, Trong HUYNH BAO, Raf APPELTANS
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Publication number: 20200312725Abstract: The disclosed technology relates to methods of fabricating field-effect transistors having channels extending in horizontal and vertical directions.Type: ApplicationFiled: March 31, 2020Publication date: October 1, 2020Inventors: Anabela Veloso, Trong Huynh Bao, Julien Ryckaert, Raf Appeltans
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Patent number: 10720363Abstract: The disclosed technology generally relates to semiconductor fabrication and more particularly to forming vertical transistor devices. In an aspect, a method of forming a vertical transistor device includes forming, on a substrate, a fin comprising a stack including a first layer, a second layer formed above the first layer and a third layer formed above the second layer. The method additionally includes forming a gate layer serving as an etch mask above the third layer. The method further includes etching the second and third layers of the fin using the gate layer as the etch mask to form a pillar. First and third layers of the pillar define a source region and a drain region, respectively, of the vertical transistor device. A second layer of the pillar defines a channel region of the vertical transistor device. The gate layer comprises a gate electrode arranged on at least one sidewall of the second layer.Type: GrantFiled: May 11, 2018Date of Patent: July 21, 2020Assignees: IMEC vzw, Vrije Universiteit BrusselInventors: Julien Ryckaert, Naoto Horiguchi, Dan Mocuta, Trong Huynh Bao
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Publication number: 20200211642Abstract: A circuit cell for a memory device or a logic device comprises: (i) first and a second logic gates having respective output nodes; and (ii) first and second memory units, each comprising (a) first and second terminals and (b) a resistive memory element and a bipolar selector connected in series between the first and second terminals, wherein the first terminals of the first and second memory units are connected to the output nodes of the first and second logic gates, respectively, wherein the resistive memory elements are configured to be switchable between first and second resistance states, and wherein in response to a switching current and the bipolar selectors are configured to be conducting in response to an absolute value of a voltage difference across the bipolar selectors exceeding a threshold voltage of the bipolar selectors and non-conducting in response to the absolute value being lower than the threshold.Type: ApplicationFiled: December 26, 2019Publication date: July 2, 2020Inventors: Trong Huynh Bao, Sushil Sakhare
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Publication number: 20200185016Abstract: According to an example embodiment an MTJ unit is provided. The MTJ unit includes: a first MTJ comprising a first free layer, a first tunnel barrier layer and a first reference layer. The first MTJ is switchable between a parallel state and an anti-parallel state through spin-torque transfer (STT). The MTJ unit comprises a second MTJ arranged above the first MTJ and comprising, a second reference layer, a second tunnel barrier layer and a second free layer. The second MTJ is switchable between a parallel state and an anti-parallel state through STT. The MTJ unit comprises a pinning layer arranged between the first reference layer and the second reference layer and configured to fix a magnetization direction of the first reference layer and the second reference layer.Type: ApplicationFiled: December 6, 2019Publication date: June 11, 2020Inventors: Sushil Sakhare, Manu Komalan Perumkunnil, Johan Swerts, Gouri Sankar Kar, Trong Huynh Bao
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Patent number: 10522552Abstract: The disclosed technology generally relates semiconductor devices and more particularly to a vertical transistor device, and a method of fabricating the same. In one aspect, the method includes providing, on a substrate, a fin formed of a stack of a first layer, a second layer and a third layer, wherein the second layer is positioned above the first layer and the third layer is positioned above the second layer. The method additionally includes forming a dielectric on the sidewalls of the first and third layers of the fin selectively against a sidewall of the second layer, and the method additionally includes forming a gate contacting layer for contacting a sidewall of the second layer. The first and third layers define a source region and a drain region, respectively, of the vertical transistor device. The second layer defines a channel region of the vertical transistor device.Type: GrantFiled: May 15, 2018Date of Patent: December 31, 2019Assignee: IMEC vzwInventors: Julien Ryckaert, Naoto Horiguchi, Dan Mocuta, Trong Huynh Bao
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Patent number: 10332588Abstract: In an aspect of the disclosed technology, a SRAM device includes a first stack of transistors and a second stack of transistors arranged on a substrate. Each of the first and second stacks includes a pull-up transistor, a pull-down transistor and a pass transistor, where each of the transistors includes a horizontally extending channel. In each of the first and second stacks, the pull-up transistor and the pull-down transistor have a common gate electrode extending vertically therebetween, and the pass transistor has a gate electrode separated from the common gate electrode. A source/drain of each of the pull-up transistor and the pull-down transistor and a source/drain of the pass transistor included in one of the first stack and the second stack are electrically interconnected with the common gate electrode of the pull-up transistor and the pull-down transistor included in the other of the first stack and the second stack.Type: GrantFiled: December 21, 2017Date of Patent: June 25, 2019Assignees: IMEC vzw, Vrije Universiteit BrusselInventors: Trong Huynh Bao, Julien Ryckaert, Praveen Raghavan, Pieter Weckx
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Patent number: 10325647Abstract: A memory cell is disclosed, comprising a static random-access memory, SRAM, bit cell, a first resistive memory element and a second resistive memory element. The first resistive memory element is connected to a first storage node of the SRAM bit cell and a first intermediate node, and the second resistive memory element connected to a second storage node of the SRAM bit cell and a second intermediate node. Each one of the first intermediate node and the second intermediate node is configured to be supplied with a first supply voltage via a first transistor and a second supply voltage via a second transistor, wherein the first transistor and the second transistor are complementary transistors separately controllable by a first word line and a second word line, respectively. Methods for operating such a memory cell are also disclosed.Type: GrantFiled: December 6, 2017Date of Patent: June 18, 2019Assignees: IMEC VZW, VRIJE UNIVERSITEIT BRUSSEL, Katholieke Universiteit Leuven, KU Leuven R&DInventors: Sushil Sakhare, Trong Huynh Bao, Manu Komalan Perumkunnil
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Publication number: 20180342524Abstract: The disclosed technology generally relates semiconductor devices and more particularly to a vertical transistor device, and a method of fabricating the same. In one aspect, the method includes providing, on a substrate, a fin formed of a stack of a first layer, a second layer and a third layer, wherein the second layer is positioned above the first layer and the third layer is positioned above the second layer. The method additionally includes forming a dielectric on the sidewalls of the first and third layers of the fin selectively against a sidewall of the second layer, and the method additionally includes forming a gate contacting layer for contacting a sidewall of the second layer. The first and third layers define a source region and a drain region, respectively, of the vertical transistor device. The second layer defines a channel region of the vertical transistor device.Type: ApplicationFiled: May 15, 2018Publication date: November 29, 2018Inventors: Julien Ryckaert, Naoto Horiguchi, Dan Mocuta, Trong Huynh Bao
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Publication number: 20180330997Abstract: The disclosed technology generally relates to semiconductor fabrication and more particularly to forming vertical transistor devices. In an aspect, a method of forming a vertical transistor device includes forming, on a substrate, a fin comprising a stack including a first layer, a second layer formed above the first layer and a third layer formed above the second layer. The method additionally includes forming a gate layer serving as an etch mask above the third layer. The method further includes etching the second and third layers of the fin using the gate layer as the etch mask to form a pillar. First and third layers of the pillar define a source region and a drain region, respectively, of the vertical transistor device. A second layer of the pillar defines a channel region of the vertical transistor device. The gate layer comprises a gate electrode arranged on at least one sidewall of the second layer.Type: ApplicationFiled: May 11, 2018Publication date: November 15, 2018Inventors: Julien Ryckaert, Naoto Horiguchi, Dan Mocuta, Trong Huynh Bao