Abstract: A clock and data recovery circuit including: means for generating a first and a second clock signal; means for receiving the first clock signal and for generating a third clock signal from the first clock signal and means for receiving the second clock signal and for generating a fourth clock signal, wherein at least one of the third and the fourth clock signals differ in phase from the first and the second clock signal respectively; means for receiving the third and fourth clock signals and a serial data stream and for generating a reconstructed serial data stream and a phase error signal; means for receiving the phase error signal and for generating a phase adjustment signal and means for receiving the phase adjustment signal by the by the clock generation circuit in a feedback loop to adjust the phases of the first and second clock signals.

Abstract: A clock and data recovery circuit including: means for generating a first and a second clock signal; means for receiving the first clock signal and for generating a third clock signal from the first clock signal and means for receiving the second clock signal and for generating a fourth clock signal, wherein at least one of the third and the fourth clock signals differ in phase from the first and the second clock signal respectively; means for receiving the third and fourth clock signals and a serial data stream and for generating a reconstructed serial data stream and a phase error signal; means for receiving the phase error signal and for generating a phase adjustment signal and means for receiving the phase adjustment signal by the by the clock generation circuit in a feedback loop to adjust the phases of the first and second clock signals.

Abstract: A clock and data recovery circuit including: means for generating a first and a second clock signal; means for receiving the first clock signal and for generating a third clock signal from the first clock signal and means for receiving the second clock signal and for generating a fourth clock signal, wherein at least one of the third and the fourth clock signals differ in phase from the first and the second clock signal respectively; means for receiving the third and fourth clock signals and a serial data stream and for generating a reconstructed serial data stream and a phase error signal; means for receiving the phase error signal and for generating a phase adjustment signal and means for receiving the phase adjustment signal by the by the clock generation circuit in a feedback loop to adjust the phases of the first and second clock signals.

Abstract: An integrated circuit and a method of reconfiguring an integrated circuit in which multiple configuration sets, each including a plurality of register settings, are stored on the chip. Selection of at least a portion of a configuration set allows for quicker and easier retrieval and loading of register settings, and reduces the complexity and size of the higher level system control program. In an alternative embodiment, at least a portion of a configuration set that is stored on the chip can be directly loaded to at least one device to be controlled to eliminate the need for the set of registers.

Abstract: A clock and data recovery circuit including: means for generating a first and a second clock signal; means for receiving the first clock signal and for generating a third clock signal from the first clock signal and means for receiving the second clock signal and for generating a fourth clock signal, wherein at least one of the third and the fourth clock signals differ in phase from the first and the second clock signal respectively; means for receiving the third and fourth clock signals and a serial data stream and for generating a reconstructed serial data stream and a phase error signal; means for receiving the phase error signal and for generating a phase adjustment signal and means for receiving the phase adjustment signal by the by the clock generation circuit in a feedback loop to adjust the phases of the first and second clock signals.

Abstract: An integrated circuit and a method of reconfiguring an integrated circuit in which multiple configuration sets, each including a plurality of register settings, are stored on the chip. Selection of at least a portion of a configuration set allows for quicker and easier retrieval and loading of register settings, and reduces the complexity and size of the higher level system control program. In an alternative embodiment, at least a portion of a configuration set that is stored on the chip can be directly loaded to at least one device to be controlled to eliminate the need for the set of registers.

Abstract: A frequency synthesizer includes a charge pump, a fractional integration counter that alters the integrated current of the charge pump, a phase frequency detector, a proportional correction circuit, and a proportional multiplier that alters the value of the current correction output by the proportional correction circuit. The fractional integration counter alters the integrated current of the charge pump based upon a user-defined input, thereby permitting increased signal-to-noise ratio at the output of the charge pump. Similarly, the proportional multiplier alters the value of the proportional current correction based upon user-defined input, thereby modifying loop dynamics within the frequency synthesizer.

Abstract: A complementary metal oxide semiconductor PLL includes an input for receiving a reference frequency and a feedback loop for determining a phase error based on the reference frequency. The feedback loop includes a calibration DAC (amplifier with a digital gain control input) and a bandwidth DAC in series. The ICO controller is well known in control theory as a PI or proportional-integral controller. A proportional path supplies a proportional signal to the calibration amplifier and an integral path supplies an integral signal (a signal that is integrated in time) to the calibration amplifier.

Abstract: The present invention provides an improved method and apparatus for independently controlling phase and frequency using an oscillator having a plurality of stages in combination with a phase selector within a digitally controlled phase-locked loop, preferably, a read phase locked loop. The present invention provides a digitally controlled variable phase of the read timing loop in read channel integrated circuits associated with data storage devices. The phase selector has a digitally controlled fine interpolator with 12 states for further fine interpolation between at least two multiplexer phase outputs to provide a single phase output selected from a range comprising at least 2&pgr; in selectable variable phase increments of 2&pgr;/96 radian. The combined oscillator with the phase selector within a phase locked loop controls phase by exact fractional increments of equally space phases of the operating frequency within the phase locked loop, therein controlling phase at all operating frequencies.

Abstract: A complementary metal oxide semiconductor PLL includes an input for receiving a reference frequency and a feedback loop for determining a phase error based on the reference frequency. The feedback loop includes a calibration DAC (amplifier with a digital gain control input) and a bandwidth DAC in series. The ICO controller is well known in control theory as a PI or proportional-integral controller. A proportional path supplies a proportional signal to the calibration amplifier and an integral path supplies an integral signal (a signal that is integrated in time) to the calibration amplifier.

Abstract: A frequency synthesizer includes a charge pump, a fractional integration counter that alters the integrated current of the charge pump, a phase frequency detector, a proportional correction circuit, and a proportional multiplier that alters the value of the current correction output by the proportional correction circuit. The fractional integration counter alters the integrated current of the charge pump based upon a user-defined input, thereby permitting increased signal-to-noise ratio at the output of the charge pump. Similarly, the proportional multiplier alters the value of the proportional current correction based upon user-defined input, thereby modifying loop dynamics within the frequency synthesizer.