Patents by Inventor Troy D. Larsen

Troy D. Larsen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250096804
    Abstract: An example apparatus includes a memory device comprising a plurality of banks of memory cells. A particular bank of memory cells among the plurality of banks includes a system processor resident on a particular bank of the plurality of banks.
    Type: Application
    Filed: December 6, 2024
    Publication date: March 20, 2025
    Inventors: Timothy P. Finkbeiner, Troy D. Larsen
  • Patent number: 12216585
    Abstract: Apparatuses and methods related to providing coherent memory access. An apparatus for providing coherent memory access can include a memory array, a first processing resource, a first cache line and a second cache line coupled to the memory array, a first cache controller, and a second cache controller. The first cache controller coupled to the first processing resource and to the first cache line can be configured to provide coherent access to data stored in the second cache line and corresponding to a memory address. A second cache controller coupled through an interface to a second processing resource external to the apparatus and coupled to the second cache line can be configured to provide coherent access to the data stored in the first cache line and corresponding to the memory address.
    Type: Grant
    Filed: March 31, 2023
    Date of Patent: February 4, 2025
    Inventors: Timothy P. Finkbeiner, Troy D. Larsen
  • Publication number: 20250037755
    Abstract: Methods and apparatuses related to using non-zero selection circuitry. For example, the non-zero selection circuitry can determine whether a first word received from a first group of sense amplifiers has at least one bit having a first binary value, such as a logical “1”. In response to the first word being determined to have at least one bit having the first binary value, the first word can be outputted from the non-zero selection circuitry and a second word can be prevented from being outputted (even if the second word is determined to have at least one bit having the first binary value) at least while the first word is being outputted.
    Type: Application
    Filed: July 3, 2024
    Publication date: January 30, 2025
    Inventors: Timothy P. Finkbeiner, Glen E. Hush, Troy A. Manning, Troy D. Larsen, Peter L. Brown
  • Publication number: 20250029651
    Abstract: Methods, systems, and devices related to performing logical operations using multiple digit lines. At least two digit lines coupled to the same sense amplifier can be used for the logical operations. For example, two word lines on one digit line and one word line on another digit line can be substantially concurrently activated to perform a particular logical operation. These three word lines are respectively coupled to memory cells configured to store either operands of operation or a reference data value for the particular logical.
    Type: Application
    Filed: July 3, 2024
    Publication date: January 23, 2025
    Inventors: Glen E. Hush, Troy A. Manning, Timothy P. Finkbeiner, Troy D. Larsen, Peter L. Brown
  • Patent number: 12191857
    Abstract: An example apparatus includes a memory device comprising a plurality of banks of memory cells. A particular bank of memory cells among the plurality of banks includes a system processor resident on a particular bank of the plurality of banks.
    Type: Grant
    Filed: August 10, 2023
    Date of Patent: January 7, 2025
    Inventors: Timothy P Finkbeiner, Troy D. Larsen
  • Publication number: 20240296124
    Abstract: Apparatuses and methods related to providing coherent memory access. An apparatus for providing coherent memory access can include a memory array, a first processing resource, a first cache line and a second cache line coupled to the memory array, a first cache controller, and a second cache controller. The first cache controller coupled to the first processing resource and to the first cache line can be configured to provide coherent access to data stored in the second cache line and corresponding to a memory address. A second cache controller coupled through an interface to a second processing resource external to the apparatus and coupled to the second cache line can be configured to provide coherent access to the data stored in the first cache line and corresponding to the memory address.
    Type: Application
    Filed: March 31, 2023
    Publication date: September 5, 2024
    Inventors: Timothy P. Finkbeiner, Troy D. Larsen
  • Publication number: 20240256448
    Abstract: Methods, systems, and devices related to sense amplifiers of a memory device serving as a Static Random Access Memory (SRAM) cache. For example, a memory array can be coupled to sense amplifiers. In a first mode, the sense amplifiers can be electrically disconnect from digit lines of the memory array. In the first mode, data and metadata of a cache line can be stored in the sense amplifiers when electrically disconnected from the number of digit lines. In the first mode, a portion of the data can be communicated, based on the metadata, from the sense amplifiers to the processing device. In a second mode, the sense amplifiers can connect to the memory array and sense data from the memory array.
    Type: Application
    Filed: January 17, 2024
    Publication date: August 1, 2024
    Inventors: Peter L. Brown, Glen E. Hush, Troy A. Manning, Timothy P. Finkbeiner, Troy D. Larsen
  • Patent number: 11954499
    Abstract: Methods, systems, and devices for operational code storage for an on-die microprocessor are described. A microprocessor may be formed on-die with a memory array. Operating code for the microprocessor may be stored in the memory array, possibly along with other data (e.g., tracking or statistical data) used or generated by the on-die microprocessor. A wear leveling algorithm may result in some number of rows within the memory array not being used to store user data at any given time, and these rows may be used to store the operating code and possibly other data for the on-die microprocessor. The on-die microprocessor may boot and run based on the operating code stored in memory array.
    Type: Grant
    Filed: August 10, 2022
    Date of Patent: April 9, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Troy A. Manning, Jonathan D. Harms, Troy D. Larsen, Glen E. Hush, Timothy P. Finkbeiner
  • Publication number: 20240113714
    Abstract: An example apparatus includes a memory device comprising a plurality of banks of memory cells. A particular bank of memory cells among the plurality of banks includes a system processor resident on a particular bank of the plurality of banks.
    Type: Application
    Filed: August 10, 2023
    Publication date: April 4, 2024
    Inventors: Timothy P Finkbeiner, Troy D. Larsen
  • Patent number: 11837315
    Abstract: Methods and devices related to transferring data between DRAM and SRAM. One method includes activating a first portion of a dynamic random access memory (DRAM), reading data from the first portion of the DRAM, latching the data from the first portion of the DRAM in one or more sense amplifiers, and writing the data from the one or more sense amplifiers to a first portion of a static random access memory (SRAM).
    Type: Grant
    Filed: June 30, 2022
    Date of Patent: December 5, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Timothy P. Finkbeiner, Troy A. Manning, Troy D. Larsen, Glen E. Hush
  • Patent number: 11728813
    Abstract: An example apparatus includes a memory device comprising a plurality of banks of memory cells. A particular bank of memory cells among the plurality of banks includes a system processor resident on a particular bank of the plurality of banks.
    Type: Grant
    Filed: June 28, 2021
    Date of Patent: August 15, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Timothy P Finkbeiner, Troy D. Larsen
  • Patent number: 11620228
    Abstract: Apparatuses and methods related to providing coherent memory access. An apparatus for providing coherent memory access can include a memory array, a first processing resource, a first cache line and a second cache line coupled to the memory array, a first cache controller, and a second cache controller. The first cache controller coupled to the first processing resource and to the first cache line can be configured to provide coherent access to data stored in the second cache line and corresponding to a memory address. A second cache controller coupled through an interface to a second processing resource external to the apparatus and coupled to the second cache line can be configured to provide coherent access to the data stored in the first cache line and corresponding to the memory address.
    Type: Grant
    Filed: June 17, 2022
    Date of Patent: April 4, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Timothy P. Finkbeiner, Troy D. Larsen
  • Publication number: 20230033704
    Abstract: Methods, systems, and devices for operational code storage for an on-die microprocessor are described. A microprocessor may be formed on-die with a memory array. Operating code for the microprocessor may be stored in the memory array, possibly along with other data (e.g., tracking or statistical data) used or generated by the on-die microprocessor. A wear leveling algorithm may result in some number of rows within the memory array not being used to store user data at any given time, and these rows may be used to store the operating code and possibly other data for the on-die microprocessor. The on-die microprocessor may boot and run based on the operating code stored in memory array.
    Type: Application
    Filed: August 10, 2022
    Publication date: February 2, 2023
    Inventors: Troy A. Manning, Jonathan D. Harms, Troy D. Larsen, Glen E. Hush, Timothy P. Finkbeiner
  • Patent number: 11556339
    Abstract: Systems and methods related to implementing vector registers in memory. A memory system for implementing vector registers in memory can include an array of memory cells, where a plurality of rows in the array serve as a plurality of vector registers as defined by an instruction set architecture. The memory system for implementing vector registers in memory can also include a processing resource configured to, responsive to receiving a command to perform a particular vector operation on a particular vector register, access a particular row of the array serving as the particular register to perform the vector operation.
    Type: Grant
    Filed: November 9, 2021
    Date of Patent: January 17, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Timothy P. Finkbeiner, Troy D. Larsen
  • Publication number: 20220335987
    Abstract: Methods and devices related to transferring data between DRAM and SRAM. One method includes activating a first portion of a dynamic random access memory (DRAM), reading data from the first portion of the DRAM, latching the data from the first portion of the DRAM in one or more sense amplifiers, and writing the data from the one or more sense amplifiers to a first portion of a static random access memory (SRAM).
    Type: Application
    Filed: June 30, 2022
    Publication date: October 20, 2022
    Inventors: Timothy P. Finkbeiner, Troy A. Manning, Troy D. Larsen, Glen E. Hush
  • Publication number: 20220318148
    Abstract: Apparatuses and methods related to providing coherent memory access. An apparatus for providing coherent memory access can include a memory array, a first processing resource, a first cache line and a second cache line coupled to the memory array, a first cache controller, and a second cache controller. The first cache controller coupled to the first processing resource and to the first cache line can be configured to provide coherent access to data stored in the second cache line and corresponding to a memory address. A second cache controller coupled through an interface to a second processing resource external to the apparatus and coupled to the second cache line can be configured to provide coherent access to the data stored in the first cache line and corresponding to the memory address.
    Type: Application
    Filed: June 17, 2022
    Publication date: October 6, 2022
    Inventors: Timothy P. Finkbeiner, Troy D. Larsen
  • Patent number: 11430539
    Abstract: Methods, systems, and devices for modifiable repair solutions for a memory array are described to support storing repair information for a memory array within the memory array itself. A memory device may include the memory array and an on-die microprocessor, where the microprocessor may retrieve the repair information from the memory array and write the repair information to repair circuitry used for identifying defective memory addresses. The microprocessor may support techniques for identifying additional defects and updating the repair information during operation of the memory array. For example, the microprocessor may identify additional defects based on errors associated with one or more memory cells of the memory array or based on testing performed on one or more memory cells of the memory array. In some cases, a host device may identify additional defects and may notify the microprocessor of the additional defects.
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: August 30, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Troy A. Manning, Troy D. Larsen, Jonathan D. Harms, Glen E. Hush, Timothy P. Finkbeiner
  • Patent number: 11422826
    Abstract: Methods, systems, and devices for operational code storage for an on-die microprocessor are described. A microprocessor may be formed on-die with a memory array. Operating code for the microprocessor may be stored in the memory array, possibly along with other data (e.g., tracking or statistical data) used or generated by the on-die microprocessor. A wear leveling algorithm may result in some number of rows within the memory array not being used to store user data at any given time, and these rows may be used to store the operating code and possibly other data for the on-die microprocessor. The on-die microprocessor may boot and run based on the operating code stored in memory array.
    Type: Grant
    Filed: May 19, 2020
    Date of Patent: August 23, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Troy A. Manning, Jonathan D. Harms, Troy D. Larsen, Glen E. Hush, Timothy P. Finkbeiner
  • Patent number: 11397688
    Abstract: Apparatuses and methods related to providing coherent memory access. An apparatus for providing coherent memory access can include a memory array, a first processing resource, a first cache line and a second cache line coupled to the memory array, a first cache controller, and a second cache controller. The first cache controller coupled to the first processing resource and to the first cache line can be configured to provide coherent access to data stored in the second cache line and corresponding to a memory address. A second cache controller coupled through an interface to a second processing resource external to the apparatus and coupled to the second cache line can be configured to provide coherent access to the data stored in the first cache line and corresponding to the memory address.
    Type: Grant
    Filed: September 4, 2020
    Date of Patent: July 26, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Timothy P. Finkbeiner, Troy D. Larsen
  • Patent number: 11380372
    Abstract: Methods and devices related to transferring data between DRAM and SRAM. One method includes activating a first portion of a dynamic random access memory (DRAM), reading data from the first portion of the DRAM, latching the data from the first portion of the DRAM in one or more sense amplifiers, and writing the data from the one or more sense amplifiers to a first portion of a static random access memory (SRAM).
    Type: Grant
    Filed: December 17, 2020
    Date of Patent: July 5, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Timothy P. Finkbeiner, Troy A. Manning, Troy D. Larsen, Glen E. Hush