Abstract: Systems and methods are disclosed herein for determining the placement of storage and non-storage cells or components, representing a semiconductor component in a design stage, on an integrated circuit die. In one embodiment, regions of a semiconductor die are analyzed with respect to the susceptibility of a region to be exposed to radiation and the distance between a storage component and a local clock buffer. The radiation, for instance, may be alpha particle radiation emitted from lead (Pb) isotopes in solder bumps formed on the integrated circuit die. The distance, spatial positioning and/or physical proximity of a selected local clock buffer and a storage component are preferably selected so that the skew between the storage component and the local clock buffer is about 30 picoseconds or less.

Abstract: Systems and methods are disclosed herein for determining the placement of a standard cell, representing a semiconductor component in a design stage, on an integrated circuit die. One embodiment of a method, among others, comprises analyzing regions of a semiconductor die with respect to the susceptibility of the region to be exposed to radiation. This method further comprises placing the standard cell in one of the analyzed regions of the semiconductor die, the standard cell being placed based on the sensitivity of the standard cell to radiation. The method may also comprise running an algorithm, e.g. using a component placement engine, for determining the placement of semiconductor components on an integrated circuit die.

Abstract: Systems and methods are disclosed herein for determining the placement of storage and non-storage cells or components, representing a semiconductor component in a design stage, on an integrated circuit die. In one embodiment, regions of a semiconductor die are analyzed with respect to the susceptibility of a region to be exposed to radiation and the distance between a storage component and a local clock buffer. The radiation, for instance, may be alpha particle radiation emitted from lead (Pb) isotopes in solder bumps formed on the integrated circuit die. The distance, spatial positioning and/or physical proximity of a selected local clock buffer and a storage component are preferably selected so that the skew between the storage component and the local clock buffer is about 30 picoseconds or less.