Patents by Inventor Troy H. Herndon
Troy H. Herndon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7323727Abstract: A method and apparatus for providing a meshed power and signal bus system on an array type integrated circuit that minimizes the size of the circuit. In a departure from the art, through-holes for the mesh system are placed in the cell array, as well as the peripheral circuits. The power and signal buses of the mesh system run in both vertical and horizontal directions across the array such that all the vertical buses lie in one metal layer, and all the horizontal buses lie in another metal layer. The buses of one layer are connected to the appropriate bus(es) of the other layer using through-holes located in the array. Once connected, the buses extend to the appropriate sense amplifier drivers. The method and apparatus are facilitated by an improved subdecoder circuit implementing a hierarchical word line structure.Type: GrantFiled: March 8, 2007Date of Patent: January 29, 2008Assignees: Hitachi, Ltd., Texas Instruments IncorporatedInventors: Goro Kitsukawa, Takesada Akiba, Hiroshi Otori, William R. McKee, Jeffrey E. Koelling, Troy H. Herndon
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Patent number: 7211842Abstract: A method and apparatus for providing a meshed power and signal bus system on an array type integrated circuit that minimizes the size of the circuit. In a departure from the art, through-holes for the mesh system are placed in the cell array, as well as the peripheral circuits. The power and signal buses of the mesh system run in both vertical and horizontal directions across the array such that all the vertical buses lie in one metal layer, and all the horizontal buses lie in another metal layer. The buses of one layer are connected to the appropriate bus(es) of the other layer using through-holes located in the array. Once connected, the buses extend to the appropriate sense amplifier drivers. The method and apparatus are facilitated by an improved subdecoder circuit implementing a hierarchical word line structure.Type: GrantFiled: June 22, 2005Date of Patent: May 1, 2007Assignees: Hitachi, Ltd., Texas Instruments IncorporatedInventors: Goro Kitsukawa, Takesada Akiba, Hiroshi Otori, William R. McKee, Jeffrey E. Koelling, Troy H. Herndon
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Patent number: 6967371Abstract: A method and apparatus for providing a meshed power and signal bus system on an array type integrated circuit that minimizes the size of the circuit. In a departure from the art, through-holes for the mesh system are placed in the cell array, as well as the peripheral circuits. The power and signal buses of the mesh system run in both vertical and horizontal directions across the array such that all the vertical buses lie in one metal layer, and all the horizontal buses lie in another metal layer. The buses of one layer are connected to the appropriate bus(es) of the other layer using through-holes located in the array. Once connected, the buses extend to the appropriate sense amplifier drivers. The method and apparatus are facilitated by an improved subdecoder circuit implementing a hierarchical word line structure.Type: GrantFiled: September 20, 2004Date of Patent: November 22, 2005Assignees: Hitachi, Ltd., Texas Instruments IncorporatedInventors: Goro Kitsukawa, Takesada Akiba, Hiroshi Otori, William R. McKee, Jeffrey E. Koelling, Troy H. Herndon
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Patent number: 6831317Abstract: A method and apparatus for providing a meshed power and signal bus system on an array type integrated circuit that minimizes the size of the circuit. In a departure from the art, through-holes for the mesh system are placed in the cell array, as well as the peripheral circuits. The power and signal buses of the mesh system run in both vertical and horizontal directions across the array such that all the vertical buses lie in one metal layer, and all the horizontal buses lie in another metal layer. The buses of one layer are connected to the appropriate bus(es) of the other layer using through-holes located in the array. Once connected, the buses extend to the appropriate sense amplifier drivers. The method and apparatus are facilitated by an improved subdecoder circuit implementing a hierarchical word line structure.Type: GrantFiled: December 10, 2002Date of Patent: December 14, 2004Assignee: Hitachi, Ltd.Inventors: Goro Kitsukawa, Takesada Akiba, Hiroshi Otori, William R. McKee, Jeffrey E. Koelling, Troy H. Herndon
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Patent number: 6815742Abstract: A method and apparatus for providing a meshed power and signal bus system on an array type integrated circuit that minimizes the size of the circuit. In a departure from the art, through-holes for the mesh system are placed in the cell array, as well as the peripheral circuits. The power and signal buses of the mesh system run in both vertical and horizontal directions across the array such that all the vertical buses lie in one metal layer, and all the horizontal buses lie in another metal layer. The buses of one layer are connected to the appropriate bus(es) of the other layer using through-holes located in the array. Once connected, the buses extend to the appropriate sense amplifier drivers. The method and apparatus are facilitated by an improved subdecoder circuit implementing a hierarchical word line structure.Type: GrantFiled: December 5, 2003Date of Patent: November 9, 2004Assignees: Hitachi, Ltd., Texas Instruments IncorporatedInventors: Goro Kitsukawa, Takesada Akiba, Hiroshi Otori, William R. McKee, Jeffrey E. Koelling, Troy H. Herndon
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Publication number: 20040129974Abstract: A method and apparatus for providing a meshed power and signal bus system on an array type integrated circuit that minimizes the size of the circuit. In a departure from the art, through-holes for the mesh system are placed in the cell array, as well as the peripheral circuits. The power and signal buses of the mesh system run in both vertical and horizontal directions across the array such that all the vertical buses lie in one metal layer, and all the horizontal buses lie in another metal layer. The buses of one layer are connected to the appropriate bus(es) of the other layer using through-holes located in the array. Once connected, the buses extend to the appropriate sense amplifier drivers. The method and apparatus are facilitated by an improved subdecoder circuit implementing a hierarchical word line structure.Type: ApplicationFiled: December 5, 2003Publication date: July 8, 2004Applicants: Hitachi, Ltd., Texas Instruments IncorporatedInventors: Goro Kitsukawa, Takesada Akiba, Hiroshi Otori, William R. McKee, Jeffrey E. Koelling, Troy H. Herndon
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Publication number: 20030067018Abstract: A method and apparatus for providing a meshed power and signal bus system on an array type integrated circuit that minimizes the size of the circuit. In a departure from the art, through-holes for the mesh system are placed in the cell array, as well as the peripheral circuits. The power and signal buses of the mesh system run in both vertical and horizontal directions across the array such that all the vertical buses lie in one metal layer, and all the horizontal buses lie in another metal layer. The buses of one layer are connected to the appropriate bus(es) of the other layer using through-holes located in the array. Once connected, the buses extend to the appropriate sense amplifier drivers. The method and apparatus are facilitated by an improved subdecoder circuit implementing a hierarchical word line structure.Type: ApplicationFiled: December 10, 2002Publication date: April 10, 2003Applicant: Hitachi, Ltd.Inventors: Goro Kitsukawa, Takesada Akiba, Hiroshi Otori, William R. McKee, Jeffrey E. Koelling, Troy H. Herndon
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Patent number: 6512257Abstract: A method and apparatus for providing a meshed power and signal bus system on an array type integrated circuit that minimizes the size of the circuit. In a departure from the art, through-holes for the mesh system are placed in the cell array, as well as the peripheral circuits. The power and signal buses of the mesh system run in both vertical and horizontal directions across the array such that all the vertical buses lie in one metal layer, and all the horizontal buses lie in another metal layer. The buses of one layer are connected to the appropriate bus(es) of the other layer using through-holes located in the array. Once connected, the buses extend to the appropriate sense amplifier drivers. The method and apparatus are facilitated by an improved subdecoder circuit implementing a hierarchical word line structure.Type: GrantFiled: April 11, 2002Date of Patent: January 28, 2003Assignees: Hitachi, Inc., Texas Instruments IncorporatedInventors: Goro Kitsukawa, Takesada Akiba, Hiroshi Otori, William R. McKee, Jeffrey E. Koelling, Troy H. Herndon
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Publication number: 20020140015Abstract: A method and apparatus for providing a meshed power and signal bus system on an array type integrated circuit that minimizes the size ofthe circuit. In a departure from the art, through-holes for the mesh system are placed in the cell array, as well as the peripheral circuits. The power and signal buses of the mesh system run in both vertical and horizontal directions across the array such that all the vertical buses lie in one metal layer, and all the horizontal buses lie in another metal layer. The buses of one layer are connected to the appropriate bus(es) of the other layer using through-holes located in the array. Once connected, the buses extend to the appropriate sense amplifier drivers. The method and apparatus are facilitated by an improved subdecoder circuit implementing a hierarchical word line structure.Type: ApplicationFiled: April 11, 2002Publication date: October 3, 2002Inventors: Goro Kitsukawa, Takesada Akiba, Hiroshi Otori, William R. McKee, Jeffrey E. Koelling, Troy H. Herndon
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Patent number: 6417091Abstract: A mask (10) includes a pattern (14) having a plurality of substantially rectangular shapes (20) arranged longitudinally in each of a plurality of substantially parallel rows (22). The rows (22) are evenly spaced apart from each other. The substantially rectangular shapes (20) in each row (22) are evenly spaced apart from each other and offset from the substantially rectangular shapes (20) in neighboring rows (22). The substantially rectangular shapes (20) define a plurality of T-shapes (24) connected to and offset from each other.Type: GrantFiled: January 4, 2001Date of Patent: July 9, 2002Assignee: Texas Instruments IncorporatedInventors: Michael P. Keleher, Jeffrey A. McKee, Troy H. Herndon, Jing-Shing Shu
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Patent number: 6396088Abstract: A method and apparatus for providing a meshed power and signal bus system on an array type integrated circuit that minimizes the size of the circuit. In a departure from the art, through-holes for the mesh system are placed in the cell array, as well as the peripheral circuits. The power and signal buses of the mesh system run in both vertical and horizontal directions across the array such that all the vertical buses lie in one metal layer, and all the horizontal buses lie in another metal layer. The buses of one layer are connected to the appropriate bus(es) of the other layer using through-holes located in the array. Once connected, the buses extend to the appropriate sense amplifier drivers. The method and apparatus are facilitated by an improved subdecoder circuit implementing a hierarchical word line structure.Type: GrantFiled: July 19, 2001Date of Patent: May 28, 2002Assignee: Hitachi, Ltd.Inventors: Goro Kitsukawa, Takesada Akiba, Hiroshi Otori, William R. McKee, Jeffrey E. Koelling, Troy H. Herndon
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Publication number: 20020000583Abstract: A method and apparatus for providing a meshed power and signal bus system on an array type integrated circuit that minimizes the size of the circuit. In a departure from the art, through-holes for the mesh system are placed in the cell array, as well as the peripheral circuits. The power and signal buses of the mesh system run in both vertical and horizontal directions across the array such that all the vertical buses lie in one metal layer, and all the horizontal buses lie in another metal layer. The buses of one layer are connected to the appropriate bus(es) of the other layer using through-holes located in the array. Once connected, the buses extend to the appropriate sense amplifier drivers. The method and apparatus are facilitated by an improved subdecoder circuit implementing a hierarchical word line structure.Type: ApplicationFiled: July 19, 2001Publication date: January 3, 2002Inventors: Goro Kitsukawa, Takesada Akiba, Hiroshi Otori, William R. McKee, Jeffrey E. Koelling, Troy H. Herndon
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Patent number: 6288925Abstract: A method and apparatus for providing a meshed power and signal bus system on an array type integrated circuit that minimizes the size of the circuit. In a departure from the art, through-holes for the mesh system are placed in the cell array, as well as the peripheral circuits. The power and signal buses of the mesh system run in both vertical and horizontal directions across the array such that all the vertical buses lie in one metal layer, and all the horizontal buses lie in another metal layer. The buses of one layer are connected to the appropriate bus(es) of the other layer using through-holes located in the array. Once connected, the buses extend to the appropriate sense amplifier drivers. The method and apparatus are facilitated by an improved subdecoder circuit implementing a hierarchical word line structure.Type: GrantFiled: February 1, 2000Date of Patent: September 11, 2001Assignees: Hitachi, LTD, Texas Instruments, Inc.Inventors: Goro Kitsukawa, Takesada Akiba, Hiroshi Otori, William R. McKee, Jeffrey E. Koelling, Troy H. Herndon
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Publication number: 20010002332Abstract: A mask (10) includes a pattern (14) having a plurality of substantially rectangular shapes (20) arranged longitudinally in each of a plurality of substantially parallel rows (22). The rows (22) are evenly spaced apart from each other. The substantially rectangular shapes (20) in each row (22) are evenly spaced apart from each other and offset from the substantially rectangular shapes (20) in neighboring rows (22). The substantially rectangular shapes (20) define a plurality of T-shapes (24) connected to and offset from each other.Type: ApplicationFiled: January 4, 2001Publication date: May 31, 2001Inventors: Michael P. Keleher, Jeffrey A. McKee, Troy H. Herndon, Jing-Shing Shu
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Patent number: 6194306Abstract: A mask (10) includes a pattern (14) having a plurality of substantially rectangular shapes (20) arranged longitudinally in each of a plurality of substantially parallel rows (22). The rows (22) are evenly spaced apart from each other. The substantially rectangular shapes (20) in each row (22) are evenly spaced apart from each other and offset from the substantially rectangular shapes (20) in neighboring rows (22). The substantially rectangular shapes (20) define a plurality of T-shapes (24) connected to and offset from each other.Type: GrantFiled: December 22, 1998Date of Patent: February 27, 2001Assignee: Texas Instruments IncorporatedInventors: Michael P. Keleher, Jeffrey A. McKee, Troy H. Herndon, Jing-Shing Shu
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Patent number: 6115279Abstract: A method and apparatus for providing a meshed power and signal bus system on an array type integrated circuit that minimizes the size of the circuit. In a departure from the art, through-holes for the mesh system are placed in the cell array, as well as the peripheral circuits. The power and signal buses of the mesh system run in both vertical and horizontal directions across the array such that all the vertical buses lie in one metal layer, and all the horizontal buses lie in another metal layer. The buses of one layer are connected to the appropriate bus(es) of the other layer using through-holes located in the array. Once connected, the buses extend to the appropriate sense amplifier drivers. The method and apparatus are facilitated by an improved subdecoder circuit implementing a hierarchical word line structure.Type: GrantFiled: October 10, 1996Date of Patent: September 5, 2000Assignee: Hitachi Ltd.Inventors: Goro Kitsukawa, Takesada Akiba, Hiroshi Otori, William R. McKee, Jeffrey E. Koelling, Troy H. Herndon
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Patent number: 6069813Abstract: A method and apparatus for providing a meshed power and signal bus system on an array type integrated circuit that minimizes the size of the circuit. In a departure from the art, through-holes for the mesh system are placed in the cell array, as well as the peripheral circuits. The power and signal buses of the mesh system run in both vertical and horizontal directions across the array such that all the vertical buses lie in one metal layer, and all the horizontal buses lie in another metal layer. The buses of one layer are connected to the appropriate bus(es) of the other layer using through-holes located in the array. Once connected, the buses extend to the appropriate sense amplifier drivers. The method and apparatus are facilitated by an improved subdecoder circuit implementing a hierarchical word line structure.Type: GrantFiled: June 11, 1999Date of Patent: May 30, 2000Assignees: Hitachi, Ltd., Texas Instruments IncorporatedInventors: Goro Kitsukawa, Takesada Akiba, Hiroshi Otori, William R. McKee, Jeffrey E. Koelling, Troy H. Herndon
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Patent number: 5953242Abstract: A method and apparatus for providing a meshed power and signal bus system on an array type integrated circuit that minimizes the size of the circuit. In a departure from the art, through-holes for the mesh system are placed in the cell array, as well as the peripheral circuits. The power and signal buses of the mesh system run in both vertical and horizontal directions across the array such that all the vertical buses lie in one metal layer, and all the horizontal buses lie in another metal layer. The buses of one layer are connected to the appropriate bus(es) of the other layer using through-holes located in the array. Once connected, the buses extend to the appropriate sense amplifier drivers. The method and apparatus are facilitated by an improved subdecoder circuit implementing a hierarchical word line structure.Type: GrantFiled: December 16, 1997Date of Patent: September 14, 1999Assignees: Hitachi Ltd., Texas Instruments IncorporatedInventors: Goro Kitsukawa, Takesada Akiba, Hiroshi Otori, William R. McKee, Jeffrey E. Koelling, Troy H. Herndon
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Patent number: 4692781Abstract: An input protection circuit for an MOS device uses a thick-oxide transistor connected as a diode between a metal bonding pad and ground. The channel width of this transistor is chosen to be sufficient to withstand large, short-duration current spikes caused by electrostatic discharge. More important, the spacing between a metal-to-silicon contact to the drain of this transistor and the channel of the transistor (where heat is generated), is chosen to be much larger than usual so the metal of the contact will not be melted by heat propagating along the silicon surface during the current spike due to ESD. This spacing feature also applies to circuits for output pads, or circuits using diode protection devices.Type: GrantFiled: June 6, 1984Date of Patent: September 8, 1987Assignee: Texas Instruments IncorporatedInventors: Robert N. Rountree, Troy H. Herndon