Abstract: Disclosed is a method wherein selective voltage binning and leakage power screening of integrated circuit (IC) chips are performed. Additionally, pre-test power-optimized bin reassignments are made on a chip-by-chip basis. Specifically, a leakage power measurement of an IC chip selected from a voltage bin can is compared to a bin-specific leakage power screen value of the next slower voltage bin. If the leakage power measurement is higher, the IC chip will be left in the voltage bin to which it is currently assigned. If the leakage power measurement is lower, the IC chip will be reassigned to that next slower voltage bin. These processes can be iteratively repeated until no slower voltage bins are available or the IC chip cannot be reassigned. IC chips can subsequently be tested according to testing parameters, including the minimum test voltages, associated with the voltage bins to which they are finally assigned.

Abstract: Disclosed is a method wherein selective voltage binning and leakage power screening of integrated circuit (IC) chips are performed. Additionally, pre-test power-optimized bin reassignments are made on a chip-by-chip basis. Specifically, a leakage power measurement of an IC chip selected from a voltage bin can is compared to a bin-specific leakage power screen value of the next slower voltage bin. If the leakage power measurement is higher, the IC chip will be left in the voltage bin to which it is currently assigned. If the leakage power measurement is lower, the IC chip will be reassigned to that next slower voltage bin. These processes can be iteratively repeated until no slower voltage bins are available or the IC chip cannot be reassigned. IC chips can subsequently be tested according to testing parameters, including the minimum test voltages, associated with the voltage bins to which they are finally assigned.

Abstract: Disclosed is a method wherein selective voltage binning and leakage power screening of integrated circuit (IC) chips are performed. Additionally, pre-test power-optimized bin reassignments are made on a chip-by-chip basis. Specifically, a leakage power measurement of an IC chip selected from a voltage bin can is compared to a bin-specific leakage power screen value of the next slower voltage bin. If the leakage power measurement is higher, the IC chip will be left in the voltage bin to which it is currently assigned. If the leakage power measurement is lower, the IC chip will be reassigned to that next slower voltage bin. These processes can be iteratively repeated until no slower voltage bins are available or the IC chip cannot be reassigned. IC chips can subsequently be tested according to testing parameters, including the minimum test voltages, associated with the voltage bins to which they are finally assigned.

Abstract: Disclosed are methods for performing threshold voltage (VT)-type transistor sensitive and/or fan-out sensitive selective voltage binning (SVB) to improve SVB accuracy and, thereby product yield and reliability. In the methods, a process distribution for an integrated circuit chip design is divided into process windows, each associated with a corresponding performance range and a corresponding minimum supply voltage. First performance measurements are acquired from first performance monitors associated with first transistors on chips manufactured according to the design. Based on the first performance measurements, the chips are assigned to groups corresponding to the process windows. Second performance measurements are also be acquired from second performance monitors associated with second transistors, which are on the chips and which have either a different VT-type or a different maximum fan-out than the first transistors.

Abstract: Methods and systems for semiconductor line scribe centering are provided. A method includes placing and measuring substantially identical test macros within a chip and in a scribe line. The method also includes establishing an estimate correlation between scribe line measurements taken during a manufacturing process and product measurements taken on a final product. The method also includes determining empirical scribe line specification limits consistent with established product screen limits. The method also includes adjusting the manufacturing process in order to optimize performance to the empirical scribe line specification limits.

Abstract: Disclosed is a method wherein selective voltage binning and leakage power screening of integrated circuit (IC) chips are performed. Additionally, pre-test power-optimized bin reassignments are made on a chip-by-chip basis. Specifically, a leakage power measurement of an IC chip selected from a voltage bin can is compared to a bin-specific leakage power screen value of the next slower voltage bin. If the leakage power measurement is higher, the IC chip will be left in the voltage bin to which it is currently assigned. If the leakage power measurement is lower, the IC chip will be reassigned to that next slower voltage bin. These processes can be iteratively repeated until no slower voltage bins are available or the IC chip cannot be reassigned. IC chips can subsequently be tested according to testing parameters, including the minimum test voltages, associated with the voltage bins to which they are finally assigned.

Abstract: An integrated circuit device includes component devices (that include primary and alternate devices) and storage elements connected to the component devices. The storage elements store different sets of repair addresses indicating which of the primary devices and alternate devices are to be enabled. Further, a controller is connected to the storage elements, and a temperature sensor is connected to the controller. The temperature sensor senses the temperature. The controller selects one of the different storage elements to select at least one of the sets of repair addresses based on the temperature sensed by the temperature sensor. The sets of repair addresses share use of at least one of the alternate devices and at least one of the primary devices.

Abstract: Methods and systems for semiconductor line scribe centering are provided. A method includes placing and measuring substantially identical test macros within a chip and in a scribe line. The method also includes establishing an estimate correlation between scribe line measurements taken during a manufacturing process and product measurements taken on a final product. The method also includes determining empirical scribe line specification limits consistent with established product screen limits. The method also includes adjusting the manufacturing process in order to optimize performance to the empirical scribe line specification limits.

Abstract: An integrated circuit device comprises component devices (that include primary and alternate devices) and storage elements connected to the component devices. The storage elements store different sets of repair addresses indicating which of the primary devices and alternate devices are to be enabled. Further, a controller is connected to the storage elements, and a temperature sensor is connected to the controller. The temperature sensor senses the temperature. The controller selects one of the different storage elements to select at least one of the sets of repair addresses based on the temperature sensed by the temperature sensor. The sets of repair addresses share use of at least one of the alternate devices and at least one of the primary devices.

Abstract: A design structure for providing optimal fuse programming conditions by which an integrated circuit chip customer may program electronic fuses in the field, i.e., outside of the manufacturing test environment. An optimal fuse programming identifier, which is correlated to optimal fuse programming conditions, may be provided to the customer in readable fashion on the customer's IC chip. Accessing the optimal fuse programming identifier on the customer's IC chip, the customer may apply a fuse programming process in the field according to one or more correlated optimal fuse programming conditions.

Abstract: A method of providing optimal fuse programming conditions by which an integrated circuit chip customer may program electronic fuses in the field, i.e., outside of the manufacturing test environment. An optimal fuse programming identifier, which is correlated to optimal fuse programming conditions, may be provided to the customer in readable fashion on the customer's IC chip. Accessing the optimal fuse programming identifier on the customer's IC chip, the customer may apply a fuse programming process in the field according to one or more correlated optimal fuse programming conditions.

Abstract: A system for performing device-specific testing and acquiring parametric data on custom integrated circuits, for example ASICs, such that each chip is tested individually without excessive test time requirements, additional silicon, or special test equipment. The testing system includes a device test structure integrated into unused backfill space in an ASIC design which tests a set of dummy devices that are identical to some of those of the ASIC. The device test structure includes control logic for designating the type of test and which device types to activate (e.g. pFETs or nFETs), a protection circuit for protecting the SPM when the test is inactive, an isolation circuit for isolating the devices under test (DUT) from any leakage current during test, and a decode circuit for providing test input (e.g. voltages) to the DUT. By controlling which devices to test and the voltage conditions of those devices, the system calculates the relative product yield and health of the line on a die by die basis.

Abstract: A method of providing optimal fuse programming conditions by which an integrated circuit chip customer may program electronic fuses in the field, i.e., outside of the manufacturing test environment. An optimal fuse programming identifier, which is correlated to optimal fuse programming conditions, may be provided to the customer in readable fashion on the customer's IC chip. Accessing the optimal fuse programming identifier on the customer's IC chip, the customer may apply a fuse programming process in the field according to one or more correlated optimal fuse programming conditions.

Abstract: A design structure for providing optimal fuse programming conditions by which an integrated circuit chip customer may program electronic fuses in the field, i.e., outside of the manufacturing test environment. An optimal fuse programming identifier, which is correlated to optimal fuse programming conditions, may be provided to the customer in readable fashion on the customer's IC chip. Accessing the optimal fuse programming identifier on the customer's IC chip, the customer may apply a fuse programming process in the field according to one or more correlated optimal fuse programming conditions.

Abstract: A system for performing device-specific testing and acquiring parametric data on custom integrated circuits, for example ASICs, such that each chip is tested individually without excessive test time requirements, additional silicon, or special test equipment. The testing system includes a device test structure integrated into unused backfill space in an ASIC design which tests a set of dummy devices that are identical to some of those of the ASIC. The device test structure includes control logic for designating the type of test and which device types to activate (e.g. pFETs or nFETs), a protection circuit for protecting the SPM when the test is inactive, an isolation circuit for isolating the devices under test (DUT) from any leakage current during test, and a decode circuit for providing test input (e.g. voltages) to the DUT. By controlling which devices to test and the voltage conditions of those devices, the system calculates the relative product yield and health of the line on a die by die basis.

Abstract: A system, method and program product for adjusting an environmental variable of a fuse blow of an electronic fuse are disclosed. A mimic NFET is coupled to a fuse blow source voltage line, a fuse blow gate voltage line, and a chip ground in the same manner as the electronic fuse, except that the mimic NFET is not attached to a poly fuse link. The on current (ion) and off current (ioff) of the mimic NFET are measured to determine a blow current of the electronic fuse. The environmental variable is adjusted based on the determined blow current.